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1. 
Cover image for Embedded System Design
Embedded System Design
Author 
Marwedel, Peter. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/0-387-30087-2
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2. 
Cover image for Ingredients for Successful System Level Design Methodology
Ingredients for Successful System Level Design Methodology
Author 
Patel, Hiren D. author. Shukla, Sandeep K. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-8472-0
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3. 
Cover image for Embedded System Design: Topics, Techniques and Trends
Embedded System Design: Topics, Techniques and Trends
Author 
Rettberg, Achim. editor. Zanella, Mauro C. editor. Dömer, Rainer. editor. Gerstlauer, Andreas. editor. Rammig, Franz J. editor.
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http://dx.doi.org/10.1007/978-0-387-72258-0
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4. 
Cover image for Embedded System Design Embedded Systems Foundations of Cyber-Physical Systems, and the Internet of Things
Embedded System Design Embedded Systems Foundations of Cyber-Physical Systems, and the Internet of Things
Author 
Marwedel, Peter. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-56045-8
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5. 
Cover image for Languages, Design Methods, and Tools for Electronic System Design Selected Contributions from FDL 2016
Languages, Design Methods, and Tools for Electronic System Design Selected Contributions from FDL 2016
Author 
Fummi, Franco. editor. Wille, Robert. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-62920-9
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6. 
Cover image for Brain-Machine Interface Closed-loop Bidirectional System Design
Brain-Machine Interface Closed-loop Bidirectional System Design
Author 
Liu, Xilin. author. Van der Spiegel, Jan. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-67940-2
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7. 
Cover image for VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers
VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers
Author 
Burg, Andreas. editor. Coṣkun, Ayṣe. editor. Guthaus, Matthew. editor. Katkoori, Srinivas. editor. Reis, Ricardo. editor.
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ONLINE(335188.1)
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http://dx.doi.org/10.1007/978-3-642-45073-0
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8. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers
Author 
Ayala, José L. editor. Shang, Delong. editor. Yakovlev, Alex. editor. SpringerLink (Online service)
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ONLINE(334136.1)
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http://dx.doi.org/10.1007/978-3-642-36157-9
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9. 
Cover image for SynDEVS Co-Design Flow A Hardware / Software Co-Design Flow Based on the Discrete Event System Specification Model of Computation
SynDEVS Co-Design Flow A Hardware / Software Co-Design Flow Based on the Discrete Event System Specification Model of Computation
Author 
Molter, H. Gregor. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-3-658-00397-5
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10. 
Cover image for System Specification and Design Languages Selected Contributions from FDL 2010
System Specification and Design Languages Selected Contributions from FDL 2010
Author 
Kaźmierski, Tom J. editor. Morawiec, Adam. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4614-1427-8
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11. 
Cover image for Introduction to Open Core Protocol Fastpath to System-on-Chip Design
Introduction to Open Core Protocol Fastpath to System-on-Chip Design
Author 
Schwaderer, W David. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4614-0103-2
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12. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers
Author 
Leuken, René. editor. Sicard, Gilles. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-3-642-17752-1
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