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1. 
Cover image for Computer-Aided Design of Microfluidic Very Large Scale Integration (mVLSI) Biochips Design Automation, Testing, and Design-for-Testability
Computer-Aided Design of Microfluidic Very Large Scale Integration (mVLSI) Biochips Design Automation, Testing, and Design-for-Testability
Author 
Hu, Kai. author. Chakrabarty, Krishnendu. author. Ho, Tsung-Yi. author. SpringerLink (Online service)
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Electronic Access 
https://doi.org/10.1007/978-3-319-56255-1
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2. 
Cover image for Advanced Digital System Design A Practical Guide to Verilog Based FPGA and ASIC Implementation
Advanced Digital System Design A Practical Guide to Verilog Based FPGA and ASIC Implementation
Author 
Roy, Shirshendu. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-031-41085-7
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3. 
Cover image for Response Feature Technology for High-Frequency Electronics. Optimization, Modeling, and Design Automation
Response Feature Technology for High-Frequency Electronics. Optimization, Modeling, and Design Automation
Author 
Pietrenko-Dabrowska, Anna. author. Koziel, Slawomir. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-031-43845-5
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4. 
Cover image for Advances in VLSI and Embedded Systems Select Proceedings of AVES 2021
Advances in VLSI and Embedded Systems Select Proceedings of AVES 2021
Author 
Darji, Anand D. editor. Joshi, Deepak. editor. Joshi, Amit. editor. Sheriff, Ray. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-981-19-6780-1
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5. 
Cover image for Hardware Security and Trust Design and Deployment of Integrated Circuits in a Threatened Environment
Hardware Security and Trust Design and Deployment of Integrated Circuits in a Threatened Environment
Author 
Sklavos, Nicolas. editor. Chaves, Ricardo. editor. Di Natale, Giorgio. editor. Regazzoni, Francesco. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-44318-8
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6. 
Cover image for VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, Revised Selected Papers
VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, Revised Selected Papers
Author 
Hollstein, Thomas. editor. Raik, Jaan. editor. Kostin, Sergei. editor. Tšertov, Anton. editor. O'Connor, Ian. editor.
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https://doi.org/10.1007/978-3-319-67104-8
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7. 
Cover image for VLSI-SoC: Design for Reliability, Security, and Low Power 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers
VLSI-SoC: Design for Reliability, Security, and Low Power 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers
Author 
Shin, Youngsoo. editor. Tsui, Chi Ying. editor. Kim, Jae-Joon. editor. Choi, Kiyoung. editor. Reis, Ricardo. editor. (orcid)0000-0001-5781-5858
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https://doi.org/10.1007/978-3-319-46097-0
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8. 
Cover image for Power Amplifiers for the S-, C-, X- and Ku-bands An EDA Perspective
Power Amplifiers for the S-, C-, X- and Ku-bands An EDA Perspective
Author 
Božanić, Mladen. author. (orcid)0000-0001-9174-0781 Sinha, Saurabh. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-28376-0
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9. 
Cover image for Circuit Design for Reliability
Circuit Design for Reliability
Author 
Reis, Ricardo. editor. Cao, Yu. editor. Wirth, Gilson. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-1-4614-4078-9
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10. 
Cover image for AIDA-CMK: Multi-Algorithm Optimization Kernel Applied to Analog IC Sizing
AIDA-CMK: Multi-Algorithm Optimization Kernel Applied to Analog IC Sizing
Author 
Lourenço, Ricardo. author. Lourenço, Nuno. author. Horta, Nuno. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-15955-3
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