Search Results for Networks on a chip.

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Subject: Networks on a chip.

Author

Al-Hashimi, Bashir M., ed.

(1)

Bertozzi, Davide.

(1)

Chattopadhyay, Santanu, contributor.

(1)

Cong-Vinh, Phan.

(1)

Coppola, Marcello.

(1)

El-Kharashi, Mohamed Watheq.

(1)

Elmiligi, Haytham.

(1)

(1)

(1)

Hsiung, Pao-Ann.

(1)

Kundu, Santanu, author.

(1)

Murray, Jacob, 1988- author.

(1)

Pande, Partha Pratim.

(1)

Shen, Jih-Sheng, 1980-

(1)

Shirazi, Behrooz A.

(1)

(1)

Language

(8)

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-

(2)

(1)

(1)

(1)

(1)

(1)

(1)

Subject

Autonomic computing.

(1)

Computer architecture.

(1)

Embedded computer systems.

(1)

Microprocessors.

(1)

ST Microelectronics.

(1)

Systems on a chip.

(1)

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1.

Cover image for Sustainable wireless network-on-chip architectures

Sustainable wireless network-on-chip architectures

Sustainable wireless network-on-chip architectures

Author

Murray, Jacob, 1988- author. Wettin, Paul. Pande, Partha Pratim. Shirazi, Behrooz A.

Preferred Shelf Number

ONLINE

Electronic Access

ScienceDirect https://www.sciencedirect.com/science/book/9780128036259

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2.

Cover image for Network-on-chip : the next generation of system-on-chip integration

Network-on-chip : the next generation of system-on-chip integration

Network-on-chip : the next generation of system-on-chip integration

Author

Kundu, Santanu, author. Chattopadhyay, Santanu, contributor.

Preferred Shelf Number

ONLINE(357050.1)

Electronic Access

Distributed by publisher. Purchase or institutional license may be required for access.

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3.

Cover image for Autonomic networking-on-chip bio-inspired specification, development, and verification

Autonomic networking-on-chip bio-inspired specification, development, and verification

Autonomic networking-on-chip bio-inspired specification, development, and verification

Author

Cong-Vinh, Phan.

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ONLINE

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4.

Cover image for Designing network on-chip architectures in the nanoscale era

Designing network on-chip architectures in the nanoscale era

Designing network on-chip architectures in the nanoscale era

Author

Flich, Jose. Bertozzi, Davide.

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5.

Cover image for Dynamic reconfigurable network-on-chip design innovations for computational processing and communication

Dynamic reconfigurable network-on-chip design innovations for computational processing and communication

Dynamic reconfigurable network-on-chip design innovations for computational processing and communication

Author

Shen, Jih-Sheng, 1980- Hsiung, Pao-Ann.

Preferred Shelf Number

ONLINE

Electronic Access

EBSCOhost http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=310487

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6.

Cover image for Networks-on-chips theory and practice

Networks-on-chips theory and practice

Networks-on-chips theory and practice

Author

Gebali, Fayez. Elmiligi, Haytham. El-Kharashi, Mohamed Watheq.

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7.

Cover image for Design of cost-efficient interconnect processing units Spidergon STNoC

Design of cost-efficient interconnect processing units Spidergon STNoC

Design of cost-efficient interconnect processing units Spidergon STNoC

Author

Coppola, Marcello.

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8.

Cover image for System-on-Chip Next generation electronics

System-on-Chip Next generation electronics

System-on-Chip Next generation electronics

Author

Al-Hashimi, Bashir M., ed.

Preferred Shelf Number

ONLINE

Electronic Access

http://dx.doi.org/10.1049/PBCS018E

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