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1. 
Cover image for Euro-Par 2018: Parallel Processing Workshops Euro-Par 2018 International Workshops, Turin, Italy, August 27-28, 2018, Revised Selected Papers
Euro-Par 2018: Parallel Processing Workshops Euro-Par 2018 International Workshops, Turin, Italy, August 27-28, 2018, Revised Selected Papers
Author 
Mencagli, Gabriele. editor. B. Heras, Dora. editor. Cardellini, Valeria. editor. Casalicchio, Emiliano. editor. Jeannot, Emmanuel. editor.
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https://doi.org/10.1007/978-3-030-10549-5
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Cover image for Applied Computer Sciences in Engineering 6th Workshop on Engineering Applications, WEA 2019, Santa Marta, Colombia, October 16–18, 2019, Proceedings
Applied Computer Sciences in Engineering 6th Workshop on Engineering Applications, WEA 2019, Santa Marta, Colombia, October 16–18, 2019, Proceedings
Author 
Figueroa-García, Juan Carlos. editor. (orcid)0000-0001-5544-5937 Duarte-González, Mario. editor. Jaramillo-Isaza, Sebastián. editor. (orcid)0000-0002-2134-772X Orjuela-Cañon, Alvaro David. editor. (orcid)0000-0002-2057-7603 Díaz-Gutierrez, Yesid. editor.
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https://doi.org/10.1007/978-3-030-31019-6
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Cover image for High Performance Computing 34th International Conference, ISC High Performance 2019, Frankfurt/Main, Germany, June 16–20, 2019, Proceedings
High Performance Computing 34th International Conference, ISC High Performance 2019, Frankfurt/Main, Germany, June 16–20, 2019, Proceedings
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Weiland, Michèle. editor. (orcid)0000-0003-4713-3073 Juckeland, Guido. editor. (orcid)0000-0002-9935-4428 Trinitis, Carsten. editor. (orcid)0000-0002-6750-3652 Sadayappan, Ponnuswamy. editor. (orcid)0000-0002-4737-2034 SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-20656-7
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Cover image for Accelerator Programming Using Directives 5th International Workshop, WACCPD 2018, Dallas, TX, USA, November 11-17, 2018, Proceedings
Accelerator Programming Using Directives 5th International Workshop, WACCPD 2018, Dallas, TX, USA, November 11-17, 2018, Proceedings
Author 
Chandrasekaran, Sunita. editor. (orcid)0000-0002-3560-9428 Juckeland, Guido. editor. (orcid)0000-0002-9935-4428 Wienke, Sandra. editor. (orcid)0000-0002-5794-3662 SpringerLink (Online service)
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Cover image for Analog Circuit Theory and Filter Design in the Digital World With an Introduction to the Morphological Method for Creative Solutions and Design
Analog Circuit Theory and Filter Design in the Digital World With an Introduction to the Morphological Method for Creative Solutions and Design
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Moschytz, George S. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-00096-7
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Cover image for Euro-Par 2019: Parallel Processing 25th International Conference on Parallel and Distributed Computing, Göttingen, Germany, August 26–30, 2019, Proceedings
Euro-Par 2019: Parallel Processing 25th International Conference on Parallel and Distributed Computing, Göttingen, Germany, August 26–30, 2019, Proceedings
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Yahyapour, Ramin. editor. (orcid)0000-0002-9057-4395 SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-29400-7
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7. 
Cover image for Fundamentals of Modern Electric Circuit Analysis and Filter Synthesis A Transfer Function Approach
Fundamentals of Modern Electric Circuit Analysis and Filter Synthesis A Transfer Function Approach
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Izadian, Afshin. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-02484-0
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8. 
Cover image for Stochastic Computing: Techniques and Applications
Stochastic Computing: Techniques and Applications
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Gross, Warren J. editor. Gaudet, Vincent C. editor. SpringerLink (Online service)
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9. 
Cover image for Transactions on High-Performance Embedded Architectures and Compilers V
Transactions on High-Performance Embedded Architectures and Compilers V
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Silvano, Cristina. editor. (orcid)0000-0003-1668-0883 Bertels, Koen. editor. (orcid)0000-0001-9310-4885 Schulte, Michael. editor. (orcid)0000-0002-0213-4155 SpringerLink (Online service)
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https://doi.org/10.1007/978-3-662-58834-5
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10. 
Cover image for Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog
Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog
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Taraate, Vaibbhav. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-981-10-8776-9
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11. 
Cover image for Supercomputing 4th Russian Supercomputing Days, RuSCDays 2018, Moscow, Russia, September 24–25, 2018, Revised Selected Papers
Supercomputing 4th Russian Supercomputing Days, RuSCDays 2018, Moscow, Russia, September 24–25, 2018, Revised Selected Papers
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Voevodin, Vladimir. editor. (orcid)0000-0001-6036-5106 Sobolev, Sergey. editor. (orcid)0000-0002-3474-8696 SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-05807-4
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12. 
Cover image for Introduction to Logic Circuits & Logic Design with VHDL
Introduction to Logic Circuits & Logic Design with VHDL
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LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-12489-2
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