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2014
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Cover image for Exploring Memory Hierarchy Design with Emerging Memory Technologies
Exploring Memory Hierarchy Design with Emerging Memory Technologies
Author 
Sun, Guangyu. author. SpringerLink (Online service)
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ONLINE
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https://doi.org/10.1007/978-3-319-00681-9
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2. 
Cover image for Trace-Based Post-Silicon Validation for VLSI Circuits
Trace-Based Post-Silicon Validation for VLSI Circuits
Author 
Liu, Xiao. author. Xu, Qiang. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-00533-1
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3. 
Cover image for Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
Author 
Noia, Brandon. author. Chakrabarty, Krishnendu. author. SpringerLink (Online service)
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ONLINE
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https://doi.org/10.1007/978-3-319-02378-6
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