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145. 
Cover image for Electrical Degradation and Breakdown in Polymers
Electrical Degradation and Breakdown in Polymers
Author 
Dissado, L. A. Fothergill, J. C.
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ONLINE
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http://dx.doi.org/10.1049/PBED009E
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146. 
Cover image for Analogue-digital ASICs Circuit techniques, design tools and applications
Analogue-digital ASICs Circuit techniques, design tools and applications
Author 
Soin, R. S., ed. Maloberti, F., ed. Franca, J., ed.
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http://dx.doi.org/10.1049/PBCS003E
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147. 
Cover image for Physics and Technology of Heterojunction Devices
Physics and Technology of Heterojunction Devices
Author 
Morgan, D. Vernon, ed. Williams, Robin H., ed.
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http://dx.doi.org/10.1049/PBED008E
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148. 
Cover image for Nanoelectronic device applications handbook
Nanoelectronic device applications handbook
Author 
IEEE International Conference on Nanotechnology (11th : 2011 : Portland, Ore.) Morris, James E. Iniewski, Krzysztof.
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149. 
Cover image for Green Software Defined Radios Enabling seamless connectivity while saving on hardware and energy
Green Software Defined Radios Enabling seamless connectivity while saving on hardware and energy
Author 
Perre, Liesbet Van der. author. Craninckx, Jan. author. Dejonghe, Antoine. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-8212-2
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150. 
Cover image for mm-Wave Silicon Technology 60 GHz and Beyond
mm-Wave Silicon Technology 60 GHz and Beyond
Author 
Niknejad, Ali M. editor. Hashemi, Hossein. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-76561-7
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151. 
Cover image for Adaptive Techniques for Dynamic Processor Optimization Theory and Practice
Adaptive Techniques for Dynamic Processor Optimization Theory and Practice
Author 
Wang, Alice. editor. Naffziger, Samuel. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-76472-6
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152. 
Cover image for SAT-Based Scalable Formal Verification Solutions
SAT-Based Scalable Formal Verification Solutions
Author 
Ganai, Malay K. author. Gupta, Aarti. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-69167-1
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153. 
Cover image for Routing Congestion in VLSI Circuits: Estimation and Optimization
Routing Congestion in VLSI Circuits: Estimation and Optimization
Author 
Saxena, Prashant. author. Shelar, Rupesh S. author. Sapatnekar, Sachin S. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/0-387-48550-3
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154. 
Cover image for Design for Manufacturability and Yield for Nano-Scale CMOS
Design for Manufacturability and Yield for Nano-Scale CMOS
Author 
Chiang, Charles C. author. Kawa, Jamil. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-5188-3
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155. 
Cover image for Modern Circuit Placement Best Practices and Results
Modern Circuit Placement Best Practices and Results
Author 
Nam, Gi-Joon. editor. Cong, Jason. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-68739-1
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156. 
Cover image for Ultra-Low Voltage Nano-Scale Memories
Ultra-Low Voltage Nano-Scale Memories
Author 
Itoh, Kiyoo. editor. Horiguchi, Masashi. editor. Tanaka, Hitoshi. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-68853-4
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