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13. 
Cover image for CATIA V5 Workbook, releases 16
CATIA V5 Workbook, releases 16
Author 
Cozzens, Richard. Metalcraft Technologies, Inc.
Preferred Shelf Number 
TA345.5.C3 C69 2006
Format: 
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14. 
Cover image for Advanced CATIA V5 workbook : release 16
Advanced CATIA V5 workbook : release 16
Author 
Cozzens, Richard.
Preferred Shelf Number 
TA345.5.C3 C69 2006
Format: 
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15. 
Cover image for Electromagnetic Compatibility of Integrated Circuits Techniques for low emission and susceptibility
Electromagnetic Compatibility of Integrated Circuits Techniques for low emission and susceptibility
Author 
Ben Dhia, Sonia. editor. Ramdani, Mohamed. editor. Sicard, Etienne. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/b137864
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16. 
Cover image for Interconnect Noise Optimization in Nanometer Technologies
Interconnect Noise Optimization in Nanometer Technologies
Author 
Elgamel, Mohamed A. author. Bayoumi, Magdy A. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/0-387-29366-3
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17. 
Cover image for Thermal and Power Management of Integrated Circuits
Thermal and Power Management of Integrated Circuits
Author 
Vassighi, Arman. author. Sachdev, Manoj. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/0-387-29749-9
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18. 
Cover image for Scalable Hardware Verification with Symbolic Simulation
Scalable Hardware Verification with Symbolic Simulation
Author 
Bertacco, Valeria. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/0-387-29906-8
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19. 
Cover image for Constraint-Based Verification
Constraint-Based Verification
Author 
Yuan, Jun. author. Pixley, Carl. author. Aziz, Adnan. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/0-387-30784-2
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20. 
Cover image for Writing Testbenches using System Verilog
Writing Testbenches using System Verilog
Author 
Bergeron, Janick. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/0-387-31275-7
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21. 
Cover image for Hardware Verification with C++ A Practitioner’s Handbook
Hardware Verification with C++ A Practitioner’s Handbook
Author 
Mintz, Mike. author. Ekendahl, Robert. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-0-387-36254-0
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22. 
Cover image for SystemVerilog for Design A Guide to Using SystemVerilog for Hardware Design and Modeling
SystemVerilog for Design A Guide to Using SystemVerilog for Hardware Design and Modeling
Author 
Sutherland, Stuart. author. Davidmann, Simon. author. Flake, Peter. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/0-387-36495-1
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23. 
Cover image for Innovation in Life Cycle Engineering and Sustainable Development
Innovation in Life Cycle Engineering and Sustainable Development
Author 
Brissaud, Daniel. editor. Tichkiewitch, Serge. editor. Zwolinski, Peggy. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/1-4020-4617-0
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24. 
Cover image for Assembly Line Design The Balancing of Mixed-Model Hybrid Assembly Lines with Genetic Algorithms
Assembly Line Design The Balancing of Mixed-Model Hybrid Assembly Lines with Genetic Algorithms
Author 
Rekiek, Brahim. author. Delchambre, Alain. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/b138846
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