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13. 
Cover image for SystemVerilog for Design A Guide to Using SystemVerilog for Hardware Design and Modeling
SystemVerilog for Design A Guide to Using SystemVerilog for Hardware Design and Modeling
Author 
Sutherland, Stuart. author. Davidmann, Simon. author. Flake, Peter. author. SpringerLink (Online service)
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ONLINE
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http://dx.doi.org/10.1007/0-387-36495-1
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14. 
Cover image for Evolvable Systems: From Biology to Hardware 6th International Conference, ICES 2005, Sitges, Spain, September 12-14, 2005. Proceedings
Evolvable Systems: From Biology to Hardware 6th International Conference, ICES 2005, Sitges, Spain, September 12-14, 2005. Proceedings
Author 
Moreno, J. Manuel. editor. Madrenas, Jordi. editor. Cosp, Jordi. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/11549703
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15. 
Cover image for Correct Hardware Design and Verification Methods 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005. Proceedings
Correct Hardware Design and Verification Methods 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005. Proceedings
Author 
Borrione, Dominique. editor. Paul, Wolfgang. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/11560548
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16. 
Cover image for SystemVerilog for Verification A Guide to Learning the Testbench Language Features
SystemVerilog for Verification A Guide to Learning the Testbench Language Features
Author 
Spear, Chris. author. Tumbush, Greg. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4614-0715-7
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17. 
Cover image for Post-Silicon and Runtime Verification for Modern Processors
Post-Silicon and Runtime Verification for Modern Processors
Author 
Wagner, Ilya. author. Bertacco, Valeria. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-8034-2
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18. 
Cover image for Quantifying and Exploring the Gap Between FPGAs and ASICs Measuring and Exploring
Quantifying and Exploring the Gap Between FPGAs and ASICs Measuring and Exploring
Author 
Kuon, Ian. author. Rose, Jonathan. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-0739-4
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19. 
Cover image for Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Author 
Patra, Priyardarsan. author. Kougianos, Elias. author. Ranganathan, Nagarajan. author. Mohanty, Saraju P. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-76474-0
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20. 
Cover image for CMOS Active Inductors and Transformers Principle, Implementation, and Applications
CMOS Active Inductors and Transformers Principle, Implementation, and Applications
Author 
Yuan, Fei. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-76479-5
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21. 
Cover image for System Verilog for Verification A Guide to Learning the Testbench Language Features
System Verilog for Verification A Guide to Learning the Testbench Language Features
Author 
Spear, Chris. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-76530-3
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22. 
Cover image for Verilog and SystemVerilog Gotchas 101 Common Coding Errors and How to Avoid Them
Verilog and SystemVerilog Gotchas 101 Common Coding Errors and How to Avoid Them
Author 
Sutherland, Stuart. author. Mills, Don. author. SpringerLink (Online service)
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ONLINE
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http://dx.doi.org/10.1007/978-0-387-71715-9
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23. 
Cover image for CMOS Current-Mode Circuits for Data Communications
CMOS Current-Mode Circuits for Data Communications
Author 
Yuan, Fei. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-47691-9
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24. 
Cover image for IT-Projektrecht Vertragliche Gestaltung und Steuerung von IT-Projekten, Best Practices, Haftung der Geschäftsleitung
IT-Projektrecht Vertragliche Gestaltung und Steuerung von IT-Projekten, Best Practices, Haftung der Geschäftsleitung
Author 
Koch, Frank A. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-3-540-73224-2
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