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313. 
Cover image for Writing Testbenches using System Verilog
Writing Testbenches using System Verilog
Author 
Bergeron, Janick. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/0-387-31275-7
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314. 
Cover image for Knowledge Enterprise: Intelligent Strategies in Product Design, Manufacturing, and Management Proceedings of PROLAMAT 2006, IFIP TC5 International Conference, June 15–17, 2006, Shanghai, China
Knowledge Enterprise: Intelligent Strategies in Product Design, Manufacturing, and Management Proceedings of PROLAMAT 2006, IFIP TC5 International Conference, June 15–17, 2006, Shanghai, China
Author 
Wang, Kesheng. editor. Kovacs, George L. editor. Wozny, Michael. editor. Fang, Minglun. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/0-387-34403-9
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315. 
Cover image for Abstraction Refinement for Large Scale Model Checking
Abstraction Refinement for Large Scale Model Checking
Author 
Wang, Chao. author. Hachtel, Gary D. author. Somenzi, Fabio. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/0-387-34600-7
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316. 
Cover image for The Core Test Wrapper Handbook Rationale and Application of IEEE Std. 1500™
The Core Test Wrapper Handbook Rationale and Application of IEEE Std. 1500™
Author 
Silva, Francisco. author. McLaurin, Teresa. author. Waayers, Tom. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/0-387-34609-0
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317. 
Cover image for A Practical Introduction to PSL
A Practical Introduction to PSL
Author 
Eisner, Cindy. author. Fisman, Dana. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-36123-9
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318. 
Cover image for Hardware Verification with C++ A Practitioner’s Handbook
Hardware Verification with C++ A Practitioner’s Handbook
Author 
Mintz, Mike. author. Ekendahl, Robert. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-0-387-36254-0
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319. 
Cover image for Innovations in Design & Decision Support Systems in Architecture and Urban Planning
Innovations in Design & Decision Support Systems in Architecture and Urban Planning
Author 
Leeuwen, Jos P. editor. Timmermans, Harry J. P. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-5060-2
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320. 
Cover image for Semiconductor Modeling For Simulating Signal, Power, and Electromagnetic Integrity
Semiconductor Modeling For Simulating Signal, Power, and Electromagnetic Integrity
Author 
Leventhal, Roy G. author. Green, Lynne. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/b104647
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321. 
Cover image for Rapid Prototyping of Digital Systems
Rapid Prototyping of Digital Systems
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Hamblen, James O. author. Hall, Tyson S. author. Furman, Michael D. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/0-387-28965-8
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322. 
Cover image for Scalable Hardware Verification with Symbolic Simulation
Scalable Hardware Verification with Symbolic Simulation
Author 
Bertacco, Valeria. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/0-387-29906-8
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323. 
Cover image for Embedded System Design
Embedded System Design
Author 
Marwedel, Peter. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/0-387-30087-2
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324. 
Cover image for SystemVerilog for Design A Guide to Using SystemVerilog for Hardware Design and Modeling
SystemVerilog for Design A Guide to Using SystemVerilog for Hardware Design and Modeling
Author 
Sutherland, Stuart. author. Davidmann, Simon. author. Flake, Peter. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/0-387-36495-1
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