Limit Search Results
Author
SpringerLink (Online service)
(46)
LaMeres, Brock J. author.
(5)
Atmaca, Eren. author.
(2)
Bhunia, Swarup. editor.
(2)
Chattopadhyay, Anupam. editor. (orcid)0000-0002-8818-6983
(2)
Language
Publication Date
-
Subject
Material Type
Shelf Location
Library
Switch to list view
Switch to thumbnail view
Select an Action
46 Results Found Subscribe to search results
000000000000DEFAULT
Print
1. 
Cover image for Designing with Xilinx® FPGAs Using Vivado
Designing with Xilinx® FPGAs Using Vivado
Author 
Churiwala, Sanjay. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-42438-5
Format: 
Availability 
Online Library~1
Available:
Copies:
2. 
Cover image for Testing of Interposer-Based 2.5D Integrated Circuits
Testing of Interposer-Based 2.5D Integrated Circuits
Author 
Wang, Ran. author. Chakrabarty, Krishnendu. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-54714-5
Format: 
Availability 
Online Library~1
Available:
Copies:
3. 
Cover image for Task Scheduling for Multi-core and Parallel Architectures Challenges, Solutions and Perspectives
Task Scheduling for Multi-core and Parallel Architectures Challenges, Solutions and Perspectives
Author 
Chen, Quan. author. Guo, Minyi. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-981-10-6238-4
Format: 
Availability 
Online Library~1
Available:
Copies:
4. 
Cover image for Hardware Protection through Obfuscation
Hardware Protection through Obfuscation
Author 
Forte, Domenic. editor. Bhunia, Swarup. editor. Tehranipoor, Mark M. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-49019-9
Format: 
Availability 
Online Library~1
Available:
Copies:
5. 
Cover image for Analog Integrated Circuit Design Automation Placement, Routing and Parasitic Extraction Techniques
Analog Integrated Circuit Design Automation Placement, Routing and Parasitic Extraction Techniques
Author 
Martins, Ricardo. author. (orcid)0000-0002-8251-1415 Lourenço, Nuno. author. Horta, Nuno. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-34060-9
Format: 
Availability 
Online Library~1
Available:
Copies:
6. 
Cover image for Emerging Technology and Architecture for Big-data Analytics
Emerging Technology and Architecture for Big-data Analytics
Author 
Chattopadhyay, Anupam. editor. (orcid)0000-0002-8818-6983 Chang, Chip Hong. editor. Yu, Hao. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-54840-1
Format: 
Availability 
Online Library~1
Available:
Copies:
7. 
Cover image for Hardware IP Security and Trust
Hardware IP Security and Trust
Author 
Mishra, Prabhat. editor. Bhunia, Swarup. editor. Tehranipoor, Mark. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-49025-0
Format: 
Availability 
Online Library~1
Available:
Copies:
8. 
Cover image for Introduction to Logic Circuits & Logic Design with Verilog
Introduction to Logic Circuits & Logic Design with Verilog
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-53883-9
Format: 
Availability 
Online Library~1
Available:
Copies:
9. 
Cover image for Automatic Methods for the Refinement of System Models From the Specification to the Implementation
Automatic Methods for the Refinement of System Models From the Specification to the Implementation
Author 
Seiter, Julia. author. Wille, Robert. author. Drechsler, Rolf. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-41480-5
Format: 
Availability 
Online Library~1
Available:
Copies:
10. 
Cover image for Digital Systems From Logic Gates to Processors
Digital Systems From Logic Gates to Processors
Author 
Deschamps, Jean-Pierre. author. Valderrama, Elena. author. Terés, Lluís. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-41198-9
Format: 
Availability 
Online Library~1
Available:
Copies:
11. 
Cover image for 3D Stacked Chips From Emerging Processes to Heterogeneous Systems
3D Stacked Chips From Emerging Processes to Heterogeneous Systems
Author 
Elfadel, Ibrahim (Abe) M. editor. (orcid)0000-0003-3220-9987 Fettweis, Gerhard. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-20481-9
Format: 
Availability 
Online Library~1
Available:
Copies:
12. 
Cover image for IP Cores Design from Specifications to Production Modeling, Verification, Optimization, and Protection
IP Cores Design from Specifications to Production Modeling, Verification, Optimization, and Protection
Author 
Mohamed, Khaled Salah. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-22035-2
Format: 
Availability 
Online Library~1
Available:
Copies:
Select an Action