Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers

Logic Synthesis for FSM-Based Control Units

Electronics System Design Techniques for Safety Critical Applications

Functional Design Errors in Digital Circuits Diagnosis, Correction and Repair

Logic Functions and Equations Examples and Exercises

Logic Synthesis for Compositional Microprogram Control Units

Practical Problems in VLSI Physical Design Automation

High-Level Synthesis From Algorithm to Digital Circuit

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedings

Layoutsynthese elektronischer Schaltungen — Grundlegende Algorithmen für die Entwurfsautomatisierung

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings

A Roadmap for Formal Property Verification