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49. 
Cover image for Operational Amplifiers Theory and Design
Operational Amplifiers Theory and Design
Author 
Huijsing, Johan. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-28127-8
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50. 
Cover image for More-than-Moore 2.5D and 3D SiP Integration
More-than-Moore 2.5D and 3D SiP Integration
Author 
Radojcic, Riko. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-52548-8
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51. 
Cover image for Parallel Sparse Direct Solver for Integrated Circuit Simulation
Parallel Sparse Direct Solver for Integrated Circuit Simulation
Author 
Chen, Xiaoming. author. Wang, Yu. author. Yang, Huazhong. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-53429-9
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52. 
Cover image for Hardware Protection through Obfuscation
Hardware Protection through Obfuscation
Author 
Forte, Domenic. editor. Bhunia, Swarup. editor. Tehranipoor, Mark M. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-49019-9
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53. 
Cover image for Hardware IP Security and Trust
Hardware IP Security and Trust
Author 
Mishra, Prabhat. editor. Bhunia, Swarup. editor. Tehranipoor, Mark. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-49025-0
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54. 
Cover image for Fundamentals of Electronic Systems Design
Fundamentals of Electronic Systems Design
Author 
Lienig, Jens. author. (orcid)0000-0002-2140-4587 Bruemmer, Hans. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-55840-0
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55. 
Cover image for Testing of Interposer-Based 2.5D Integrated Circuits
Testing of Interposer-Based 2.5D Integrated Circuits
Author 
Wang, Ran. author. Chakrabarty, Krishnendu. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-54714-5
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56. 
Cover image for New Data Structures and Algorithms for Logic Synthesis and Verification
New Data Structures and Algorithms for Logic Synthesis and Verification
Author 
Amaru, Luca Gaetano. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-43174-1
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57. 
Cover image for Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
Author 
Lourenço, Nuno. author. Martins, Ricardo. author. (orcid)0000-0002-8251-1415 Horta, Nuno. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-42037-0
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58. 
Cover image for Formal Verification of Simulink/Stateflow Diagrams A Deductive Approach
Formal Verification of Simulink/Stateflow Diagrams A Deductive Approach
Author 
Zhan, Naijun. author. Wang, Shuling. author. (orcid)0000-0002-2798-2660 Zhao, Hengjun. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-47016-0
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59. 
Cover image for The Dark Side of Silicon Energy Efficient Computing in the Dark Silicon Era
The Dark Side of Silicon Energy Efficient Computing in the Dark Silicon Era
Author 
Rahmani, Amir M. editor. Liljeberg, Pasi. editor. Hemani, Ahmed. editor. Jantsch, Axel. editor. Tenhunen, Hannu. editor.
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https://doi.org/10.1007/978-3-319-31596-6
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60. 
Cover image for Introduction to Logic Circuits & Logic Design with VHDL
Introduction to Logic Circuits & Logic Design with VHDL
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-34195-8
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