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1. 
Cover image for Fundamentals of IP and SoC Security Design, Verification, and Debug
Fundamentals of IP and SoC Security Design, Verification, and Debug
Author 
Bhunia, Swarup. editor. Ray, Sandip. editor. Sur-Kolay, Susmita. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-50057-7
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2. 
Cover image for Fundamentals of Computer Architecture and Design
Fundamentals of Computer Architecture and Design
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Bindal, Ahmet. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-25811-9
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3. 
Cover image for Analog Integrated Circuit Design Automation Placement, Routing and Parasitic Extraction Techniques
Analog Integrated Circuit Design Automation Placement, Routing and Parasitic Extraction Techniques
Author 
Martins, Ricardo. author. (orcid)0000-0002-8251-1415 Lourenço, Nuno. author. Horta, Nuno. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-34060-9
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4. 
Cover image for RFID Security A Lightweight Paradigm
RFID Security A Lightweight Paradigm
Author 
Khattab, Ahmed. author. Jeddi, Zahra. author. Amini, Esmaeil. author. Bayoumi, Magdy. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-47545-5
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5. 
Cover image for Computing Platforms for Software-Defined Radio
Computing Platforms for Software-Defined Radio
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Hussain, Waqar. editor. Nurmi, Jari. editor. Isoaho, Jouni. editor. Garzia, Fabio. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-49679-5
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6. 
Cover image for Automatic Methods for the Refinement of System Models From the Specification to the Implementation
Automatic Methods for the Refinement of System Models From the Specification to the Implementation
Author 
Seiter, Julia. author. Wille, Robert. author. Drechsler, Rolf. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-41480-5
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7. 
Cover image for Formal Verification of Simulink/Stateflow Diagrams A Deductive Approach
Formal Verification of Simulink/Stateflow Diagrams A Deductive Approach
Author 
Zhan, Naijun. author. Wang, Shuling. author. (orcid)0000-0002-2798-2660 Zhao, Hengjun. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-47016-0
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8. 
Cover image for Designing with Xilinx® FPGAs Using Vivado
Designing with Xilinx® FPGAs Using Vivado
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Churiwala, Sanjay. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-42438-5
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9. 
Cover image for Digital Systems From Logic Gates to Processors
Digital Systems From Logic Gates to Processors
Author 
Deschamps, Jean-Pierre. author. Valderrama, Elena. author. Terés, Lluís. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-41198-9
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10. 
Cover image for Model-Implementation Fidelity in Cyber Physical System Design
Model-Implementation Fidelity in Cyber Physical System Design
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Molnos, Anca. editor. Fabre, Christian. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-47307-9
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11. 
Cover image for Testing of Interposer-Based 2.5D Integrated Circuits
Testing of Interposer-Based 2.5D Integrated Circuits
Author 
Wang, Ran. author. Chakrabarty, Krishnendu. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-54714-5
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12. 
Cover image for New Data Structures and Algorithms for Logic Synthesis and Verification
New Data Structures and Algorithms for Logic Synthesis and Verification
Author 
Amaru, Luca Gaetano. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-43174-1
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