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49. 
Cover image for On-Chip Interconnect with aelite Composable and Predictable Systems
On-Chip Interconnect with aelite Composable and Predictable Systems
Author 
Hansson, Andreas. author. Goossens, Kees. author. SpringerLink (Online service)
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ONLINE
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http://dx.doi.org/10.1007/978-1-4419-6865-4
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50. 
Cover image for Low Power Networks-on-Chip
Low Power Networks-on-Chip
Author 
Silvano, Cristina. editor. Lajolo, Marcello. editor. Palermo, Gianluca. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-6911-8
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51. 
Cover image for Analog Layout Synthesis A Survey of Topological Approaches
Analog Layout Synthesis A Survey of Topological Approaches
Author 
Graeb, Helmut E. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-6932-3
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52. 
Cover image for Digitally-Assisted Analog and RF CMOS Circuit Design for Software-Defined Radio
Digitally-Assisted Analog and RF CMOS Circuit Design for Software-Defined Radio
Author 
Okada, Kenichi. editor. Kousai, Shouhei. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-8514-9
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53. 
Cover image for The Simple Art of SoC Design Closing the Gap between RTL and ESL
The Simple Art of SoC Design Closing the Gap between RTL and ESL
Author 
Keating, Michael. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-8586-6
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54. 
Cover image for Formal Development of a Network-Centric RTOS Software Engineering for Reliable Embedded Systems
Formal Development of a Network-Centric RTOS Software Engineering for Reliable Embedded Systems
Author 
Verhulst, Eric. author. Boute, Raymond T. author. Faria, José Miguel Sampaio. author. Sputh, Bernhard H.C. author. Mezhuyev, Vitaliy. author.
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http://dx.doi.org/10.1007/978-1-4419-9736-4
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55. 
Cover image for Programming Many-Core Chips
Programming Many-Core Chips
Author 
Vajda, András. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-9739-5
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56. 
Cover image for Reconfigurable Computing From FPGAs to Hardware/Software Codesign
Reconfigurable Computing From FPGAs to Hardware/Software Codesign
Author 
Cardoso, João M. P. editor. Hübner, Michael. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4614-0061-5
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57. 
Cover image for VLSI Physical Design: From Graph Partitioning to Timing Closure
VLSI Physical Design: From Graph Partitioning to Timing Closure
Author 
Kahng, Andrew B. author. Lienig, Jens. author. Markov, Igor L. author. Hu, Jin. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-90-481-9591-6
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58. 
Cover image for Low-Power High-Resolution Analog to Digital Converters Design, Test and Calibration
Low-Power High-Resolution Analog to Digital Converters Design, Test and Calibration
Author 
Zjajo, Amir. author. Pineda de Gyvez, José. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-90-481-9725-5
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59. 
Cover image for Regular Nanofabrics in Emerging Technologies Design and Fabrication Methods for Nanoscale Digital Circuits
Regular Nanofabrics in Emerging Technologies Design and Fabrication Methods for Nanoscale Digital Circuits
Author 
Ben Jamaa, M. Haykel. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-94-007-0650-7
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60. 
Cover image for C Compilers for ASIPs Automatic Compiler Generation with LISA
C Compilers for ASIPs Automatic Compiler Generation with LISA
Author 
Hohenauer, Manuel. author. Leupers, Rainer. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4419-1176-6
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