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49. 
Cover image for Advances in Design and Specification Languages for Embedded Systems Selected Contributions from FDL'06
Advances in Design and Specification Languages for Embedded Systems Selected Contributions from FDL'06
Author 
Huss, Sorin A. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-6149-3
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50. 
Cover image for Global Specification and Validation of Embedded Systems Integrating Heterogeneous Components
Global Specification and Validation of Embedded Systems Integrating Heterogeneous Components
Author 
Nicolescu, G. editor. Jerraya, A. A. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-6153-0
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51. 
Cover image for Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems Proceedings of the GM R&D Workshop, Bangalore, India, January 2007
Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems Proceedings of the GM R&D Workshop, Bangalore, India, January 2007
Author 
Ramesh, S. editor. Sampath, Prahladavaradan. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-6254-4
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52. 
Cover image for Processor Design System-on-Chip Computing for ASICs and FPGAs
Processor Design System-on-Chip Computing for ASICs and FPGAs
Author 
Nurmi, Jari. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-5530-0
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53. 
Cover image for Designing Embedded Processors A Low Power Perspective
Designing Embedded Processors A Low Power Perspective
Author 
Henkel, Jörg. editor. Parameswaran, Sri. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-5869-1
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54. 
Cover image for Optimized ASIP Synthesis from Architecture Description Language Models
Optimized ASIP Synthesis from Architecture Description Language Models
Author 
Schliebusch, Oliver. author. Meyr, Heinrich. author. Leupers, Rainer. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-5686-4
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55. 
Cover image for Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
Author 
Kogel, Tim. author. Leupers, Rainer. author. Meyr, Heinrich. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/1-4020-4826-2
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56. 
Cover image for FPGA Implementations of Neural Networks
FPGA Implementations of Neural Networks
Author 
Omondi, Amos R. editor. Rajapakse, Jagath C. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/0-387-28487-7
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57. 
Cover image for Platform Based Design at the Electronic System Level Industry Perspectives and Experiences
Platform Based Design at the Electronic System Level Industry Perspectives and Experiences
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Burton, Mark. author. Morawiec, Adam. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/1-4020-5138-7
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58. 
Cover image for UML for SOC Design
UML for SOC Design
Author 
Martin, Grant. editor. Müller, Wolfgang. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/b135980
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59. 
Cover image for System Level Design of Reconfigurable Systems-on-Chip
System Level Design of Reconfigurable Systems-on-Chip
Author 
Voros, Nikolaos S. editor. Masselos, Konstantinos. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/b136832
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60. 
Cover image for Advances in Design and Specification Languages for SoCs Selected Contributions from FDL’04
Advances in Design and Specification Languages for SoCs Selected Contributions from FDL’04
Author 
Boulet, Pierre. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/b136935
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