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1. 
Cover image for Source-Synchronous Networks-On-Chip Circuit and Architectural Interconnect Modeling
Source-Synchronous Networks-On-Chip Circuit and Architectural Interconnect Modeling
Author 
Mandal, Ayan. author. Khatri, Sunil P. author. Mahapatra, Rabi. author. SpringerLink (Online service)
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Electronic Access 
https://doi.org/10.1007/978-1-4614-9405-8
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2. 
Cover image for Logic Synthesis for Genetic Diseases Modeling Disease Behavior Using Boolean Networks
Logic Synthesis for Genetic Diseases Modeling Disease Behavior Using Boolean Networks
Author 
Lin, Pey-Chang Kent. author. Khatri, Sunil P. author. SpringerLink (Online service)
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Electronic Access 
https://doi.org/10.1007/978-1-4614-9429-4
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3. 
Cover image for Analysis and Design of Resilient VLSI Circuits Mitigating Soft Errors and Process Variations
Analysis and Design of Resilient VLSI Circuits Mitigating Soft Errors and Process Variations
Author 
Garg, Rajesh. author. Khatri, Sunil P. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-1-4419-0931-2
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4. 
Cover image for Hardware Acceleration of EDA Algorithms Custom ICs, FPGAs and GPUs
Hardware Acceleration of EDA Algorithms Custom ICs, FPGAs and GPUs
Author 
Gulati, Kanupriya. author. Khatri, Sunil P. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-1-4419-0944-2
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5. 
Cover image for On and Off-Chip Crosstalk Avoidance in VLSI Design
On and Off-Chip Crosstalk Avoidance in VLSI Design
Author 
Duan, Chunjie. author. LaMeres, Brock J. author. Khatri, Sunil P. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-1-4419-0947-3
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6. 
Cover image for Minimizing and Exploiting Leakage in VLSI Design
Minimizing and Exploiting Leakage in VLSI Design
Author 
Jayakumar, Nikhil. author. Paul, Suganth. author. Garg, Rajesh. author. Gulati, Kanupriya. author. Khatri, Sunil P. author.
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-1-4419-0950-3
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