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Cover image for Euro-Par 2018: Parallel Processing Workshops Euro-Par 2018 International Workshops, Turin, Italy, August 27-28, 2018, Revised Selected Papers
Euro-Par 2018: Parallel Processing Workshops Euro-Par 2018 International Workshops, Turin, Italy, August 27-28, 2018, Revised Selected Papers
Author 
Mencagli, Gabriele. editor. B. Heras, Dora. editor. Cardellini, Valeria. editor. Casalicchio, Emiliano. editor. Jeannot, Emmanuel. editor.
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https://doi.org/10.1007/978-3-030-10549-5
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2. 
Cover image for Logic Functions and Equations Binary Models for Computer Science
Logic Functions and Equations Binary Models for Computer Science
Author 
Posthoff, Christian. author. Steinbach, Bernd. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-02420-8
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Cover image for Computer Engineering and Technology 22nd CCF Conference, NCCET 2018, Yinchuan, China, August 15–17, 2018, Revised Selected Papers
Computer Engineering and Technology 22nd CCF Conference, NCCET 2018, Yinchuan, China, August 15–17, 2018, Revised Selected Papers
Author 
Xu, Weixia. editor. Xiao, Liquan. editor. Li, Jinwen. editor. Zhu, Zhenzhen. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-981-13-5919-4
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Cover image for Euro-Par 2019: Parallel Processing 25th International Conference on Parallel and Distributed Computing, Göttingen, Germany, August 26–30, 2019, Proceedings
Euro-Par 2019: Parallel Processing 25th International Conference on Parallel and Distributed Computing, Göttingen, Germany, August 26–30, 2019, Proceedings
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Yahyapour, Ramin. editor. (orcid)0000-0002-9057-4395 SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-29400-7
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5. 
Cover image for Analog Circuit Theory and Filter Design in the Digital World With an Introduction to the Morphological Method for Creative Solutions and Design
Analog Circuit Theory and Filter Design in the Digital World With an Introduction to the Morphological Method for Creative Solutions and Design
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Moschytz, George S. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-00096-7
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6. 
Cover image for Introduction to Digital Systems Design
Introduction to Digital Systems Design
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Donzellini, Giuliano. author. Oneto, Luca. author. Ponta, Domenico. author. Anguita, Davide. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-92804-3
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Cover image for Tools and Algorithms for the Construction and Analysis of Systems 25th International Conference, TACAS 2019, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2019, Prague, Czech Republic, April 6–11, 2019, Proceedings, Part II
Tools and Algorithms for the Construction and Analysis of Systems 25th International Conference, TACAS 2019, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2019, Prague, Czech Republic, April 6–11, 2019, Proceedings, Part II
Author 
Vojnar, Tomáš. editor. (orcid)0000-0002-2746-8792 Zhang, Lijun. editor. (orcid)0000-0002-3692-2088 SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-17465-1
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8. 
Cover image for Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms A Cross-layer Approach
Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms A Cross-layer Approach
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Fornaciari, William. editor. Soudris, Dimitrios. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-319-91962-1
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9. 
Cover image for Transactions on High-Performance Embedded Architectures and Compilers V
Transactions on High-Performance Embedded Architectures and Compilers V
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Silvano, Cristina. editor. (orcid)0000-0003-1668-0883 Bertels, Koen. editor. (orcid)0000-0001-9310-4885 Schulte, Michael. editor. (orcid)0000-0002-0213-4155 SpringerLink (Online service)
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https://doi.org/10.1007/978-3-662-58834-5
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10. 
Cover image for Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog
Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog
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Taraate, Vaibbhav. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-981-10-8776-9
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11. 
Cover image for Variant Construction from Theoretical Foundation to Applications
Variant Construction from Theoretical Foundation to Applications
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Zheng, Jeffrey. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-981-13-2282-2
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12. 
Cover image for Introduction to Logic Circuits & Logic Design with Verilog
Introduction to Logic Circuits & Logic Design with Verilog
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LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-13605-5
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