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1. 
Cover image for Routing Algorithms in Networks-on-Chip
Routing Algorithms in Networks-on-Chip
Author 
Palesi, Maurizio. editor. Daneshtalab, Masoud. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-1-4614-8274-1
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2. 
Cover image for Pipelined Multiprocessor System-on-Chip for Multimedia
Pipelined Multiprocessor System-on-Chip for Multimedia
Author 
Javaid, Haris. author. Parameswaran, Sri. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-01113-4
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3. 
Cover image for Machine Learning Support for Fault Diagnosis of System-on-Chip
Machine Learning Support for Fault Diagnosis of System-on-Chip
Author 
Girard, Patrick. editor. Blanton, Shawn. editor. Wang, Li-C. editor. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-031-19639-3
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4. 
Cover image for On-Chip Training NPU - Algorithm, Architecture and SoC Design
On-Chip Training NPU - Algorithm, Architecture and SoC Design
Author 
Han, Donghyeon. author. Yoo, Hoi-Jun. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-031-34237-0
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5. 
Cover image for Security Policy in System-on-Chip Designs Specification, Implementation and Verification
Security Policy in System-on-Chip Designs Specification, Implementation and Verification
Author 
Ray, Sandip. author. Basak, Abhishek. author. Bhunia, Swarup. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-93464-8
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6. 
Cover image for Analysis and Design of Networks-on-Chip Under High Process Variation
Analysis and Design of Networks-on-Chip Under High Process Variation
Author 
Ezz-Eldin, Rabab. author. El-Moursy, Magdy Ali. author. Hamed, Hesham F. A. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-25766-2
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7. 
Cover image for Microarchitecture of Network-on-Chip Routers A Designer's Perspective
Microarchitecture of Network-on-Chip Routers A Designer's Perspective
Author 
Dimitrakopoulos, Giorgos. author. Psarras, Anastasios. author. Seitanidis, Ioannis. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-1-4614-4301-8
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8. 
Cover image for Debugging Systems-on-Chip Communication-centric and Abstraction-based Techniques
Debugging Systems-on-Chip Communication-centric and Abstraction-based Techniques
Author 
Vermeulen, Bart. author. Goossens, Kees. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-06242-6
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9. 
Cover image for Models, Methods, and Tools for Complex Chip Design Selected Contributions from FDL 2012
Models, Methods, and Tools for Complex Chip Design Selected Contributions from FDL 2012
Author 
Haase, Jan. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-01418-0
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10. 
Cover image for Source-Synchronous Networks-On-Chip Circuit and Architectural Interconnect Modeling
Source-Synchronous Networks-On-Chip Circuit and Architectural Interconnect Modeling
Author 
Mandal, Ayan. author. Khatri, Sunil P. author. Mahapatra, Rabi. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-1-4614-9405-8
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11. 
Cover image for Single- and multi-chip microcontroller interfacing for the Motorola 68HC12
Single- and multi-chip microcontroller interfacing for the Motorola 68HC12
Author 
Lipovski, G. Jack.
Preferred Shelf Number 
ONLINE
Electronic Access 
ScienceDirect http://www.sciencedirect.com/science/book/9780124518308
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12. 
Cover image for Design of cost-efficient interconnect processing units : Spidergon STNoC
Design of cost-efficient interconnect processing units : Spidergon STNoC
Author 
Coppola, Marcello.
Preferred Shelf Number 
TK5105.546 .D47 2009
Electronic Access 
Click here to view.
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