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1. 
Cover image for VLSI Design and Test 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers
VLSI Design and Test 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers
Author 
Kaushik, Brajesh Kumar. editor. Dasgupta, Sudeb. editor. Singh, Virendra. editor. (orcid)0000-0002-9113-5167 SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-981-10-7470-7
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2. 
Cover image for VLSI Design and Test 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Revised Selected Papers
VLSI Design and Test 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Revised Selected Papers
Author 
Gaur, Manoj Singh. editor. Zwolinski, Mark. editor. Laxmi, Vijay. editor. Boolchandani, Dharmendra. editor. Sing, Virendra. editor.
Preferred Shelf Number 
ONLINE(335156.1)
Electronic Access 
http://dx.doi.org/10.1007/978-3-642-42024-5
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3. 
Cover image for System-Level Validation High-Level Modeling and Directed Test Generation Techniques
System-Level Validation High-Level Modeling and Directed Test Generation Techniques
Author 
Chen, Mingsong. author. Qin, Xiaoke. author. Koo, Heon-Mo. author. Mishra, Prabhat. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE(331265.1)
Electronic Access 
http://dx.doi.org/10.1007/978-1-4614-1359-2
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4. 
Cover image for Handbook of Computer Architecture
Handbook of Computer Architecture
Author 
Chattopadhyay, Anupam. editor. (orcid)0000-0002-8818-6983 SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-981-97-9314-3
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5. 
Cover image for Integrated Circuit Design Tape-out Process with Open-Source Tools
Integrated Circuit Design Tape-out Process with Open-Source Tools
Author 
Ortega Cisneros, Susana. author. Baungarten Leon, Emilio Isaac. author. (orcid)0000-0001-6243-219X Mejia Alvarez, Pedro. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-031-92108-7
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6. 
Cover image for Towards Heterogeneous Multi-core Systems-on-Chip for Edge Machine Learning Journey from Single-core Acceleration to Multi-core Heterogeneous Systems
Towards Heterogeneous Multi-core Systems-on-Chip for Edge Machine Learning Journey from Single-core Acceleration to Multi-core Heterogeneous Systems
Author 
Jain, Vikram. author. (orcid)0000-0002-1267-1683 Verhelst, Marian. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-031-38230-7
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7. 
Cover image for Machine Learning Support for Fault Diagnosis of System-on-Chip
Machine Learning Support for Fault Diagnosis of System-on-Chip
Author 
Girard, Patrick. editor. Blanton, Shawn. editor. Wang, Li-C. editor. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-031-19639-3
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8. 
Cover image for The Dark Side of Silicon Energy Efficient Computing in the Dark Silicon Era
The Dark Side of Silicon Energy Efficient Computing in the Dark Silicon Era
Author 
Rahmani, Amir M. editor. Liljeberg, Pasi. editor. Hemani, Ahmed. editor. Jantsch, Axel. editor. Tenhunen, Hannu. editor.
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-31596-6
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9. 
Cover image for More-than-Moore 2.5D and 3D SiP Integration
More-than-Moore 2.5D and 3D SiP Integration
Author 
Radojcic, Riko. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-52548-8
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10. 
Cover image for Hardware Security and Trust Design and Deployment of Integrated Circuits in a Threatened Environment
Hardware Security and Trust Design and Deployment of Integrated Circuits in a Threatened Environment
Author 
Sklavos, Nicolas. editor. Chaves, Ricardo. editor. Di Natale, Giorgio. editor. Regazzoni, Francesco. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-44318-8
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11. 
Cover image for Testing of Interposer-Based 2.5D Integrated Circuits
Testing of Interposer-Based 2.5D Integrated Circuits
Author 
Wang, Ran. author. Chakrabarty, Krishnendu. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-54714-5
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12. 
Cover image for The Boundary-Scan Handbook
The Boundary-Scan Handbook
Author 
Parker, Kenneth P. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
https://doi.org/10.1007/978-3-319-01174-5
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