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1. 
Cover image for Quick Start Guide to Verilog
Quick Start Guide to Verilog
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-031-44104-2
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2. 
Cover image for Introduction to Logic Circuits & Logic Design with Verilog
Introduction to Logic Circuits & Logic Design with Verilog
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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ONLINE
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https://doi.org/10.1007/978-3-031-43946-9
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3. 
Cover image for Quick Start Guide to VHDL
Quick Start Guide to VHDL
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-031-42543-1
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4. 
Cover image for Introduction to Logic Circuits & Logic Design with VHDL
Introduction to Logic Circuits & Logic Design with VHDL
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-031-42547-9
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5. 
Cover image for Active Object Languages: Current Research Trends
Active Object Languages: Current Research Trends
Author 
de Boer, Frank. editor. Damiani, Ferruccio. editor. (orcid)0000-0001-8109-1706 Hähnle, Reiner. editor. Broch Johnsen, Einar. editor. (orcid)0000-0001-5382-3949 Kamburjan, Eduard. editor. (orcid)0000-0002-0996-2543
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https://doi.org/10.1007/978-3-031-51060-1
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6. 
Cover image for Fundamentals of Modern Electric Circuit Analysis and Filter Synthesis A Transfer Function Approach
Fundamentals of Modern Electric Circuit Analysis and Filter Synthesis A Transfer Function Approach
Author 
Izadian, Afshin. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-031-21908-5
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7. 
Cover image for Software Defined Chips Volume II
Software Defined Chips Volume II
Author 
Liu, Leibo. author. Wei, Shaojun. author. Zhu, Jianfeng. author. Deng, Chenchen. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-981-19-7636-0
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8. 
Cover image for Computer Engineering and Technology 22nd CCF Conference, NCCET 2018, Yinchuan, China, August 15–17, 2018, Revised Selected Papers
Computer Engineering and Technology 22nd CCF Conference, NCCET 2018, Yinchuan, China, August 15–17, 2018, Revised Selected Papers
Author 
Xu, Weixia. editor. Xiao, Liquan. editor. Li, Jinwen. editor. Zhu, Zhenzhen. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-981-13-5919-4
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9. 
Cover image for Introduction to Logic Circuits & Logic Design with Verilog
Introduction to Logic Circuits & Logic Design with Verilog
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-13605-5
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10. 
Cover image for Quick Start Guide to Verilog
Quick Start Guide to Verilog
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-10552-5
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11. 
Cover image for High-Performance Modelling and Simulation for Big Data Applications Selected Results of the COST Action IC1406 cHiPSet
High-Performance Modelling and Simulation for Big Data Applications Selected Results of the COST Action IC1406 cHiPSet
Author 
Kołodziej, Joanna. editor. (orcid)0000-0002-5181-8713 González-Vélez, Horacio. editor. (orcid)0000-0003-0241-6053 SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-16272-6
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12. 
Cover image for Architecture of Computing Systems – ARCS 2019 32nd International Conference, Copenhagen, Denmark, May 20–23, 2019, Proceedings
Architecture of Computing Systems – ARCS 2019 32nd International Conference, Copenhagen, Denmark, May 20–23, 2019, Proceedings
Author 
Schoeberl, Martin. editor. Hochberger, Christian. editor. Uhrig, Sascha. editor. Brehm, Jürgen. editor. Pionteck, Thilo. editor. (orcid)0000-0001-6518-1226
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https://doi.org/10.1007/978-3-030-18656-2
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