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721. 
Cover image for New Methods of Concurrent Checking
New Methods of Concurrent Checking
Author 
Göessel, Michael. author. Ocheretny, Vitaly. author. Sogomonyan, Egor. author. Marienfeld, Daniel. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-1-4020-8420-1
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722. 
Cover image for Digital VLSI Design with Verilog A Textbook from Silicon Valley Technical Institute
Digital VLSI Design with Verilog A Textbook from Silicon Valley Technical Institute
Author 
Williams, John. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-8446-1
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723. 
Cover image for Low-Power High-Speed ADCs for Nanometer CMOS Integration
Low-Power High-Speed ADCs for Nanometer CMOS Integration
Author 
Cao, Zhiheng. author. Yan, Shouli. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-8450-8
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724. 
Cover image for Ingredients for Successful System Level Design Methodology
Ingredients for Successful System Level Design Methodology
Author 
Patel, Hiren D. author. Shukla, Sandeep K. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-8472-0
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725. 
Cover image for Analysis and Design of Quadrature Oscillators
Analysis and Design of Quadrature Oscillators
Author 
Oliveira, Luis B. author. Fernandes, Jorge R. author. Filanovsky, Igor M. author. Verhoeven, Chris J.M. author. Silva, Manuel M. author.
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http://dx.doi.org/10.1007/978-1-4020-8516-1
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726. 
Cover image for Generating Hardware Assertion Checkers For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
Generating Hardware Assertion Checkers For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
Author 
Boulé, Marc. author. Zilic, Zeljko. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-8586-4
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727. 
Cover image for High-Level Synthesis From Algorithm to Digital Circuit
High-Level Synthesis From Algorithm to Digital Circuit
Author 
Coussy, Philippe. editor. Morawiec, Adam. editor. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-8588-8
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728. 
Cover image for Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms
Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms
Author 
Wieferink, Andreas. author. Meyr, Heinrich. author. Leupers, Rainer. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-8652-6
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729. 
Cover image for The NeuroProcessor An Integrated Interface to Biological Neural Networks
The NeuroProcessor An Integrated Interface to Biological Neural Networks
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Perelman, Yevgeny. author. Ginosar, Ran. author. SpringerLink (Online service)
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http://dx.doi.org/10.1007/978-1-4020-8726-4
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730. 
Cover image for Performance-based earned value
Performance-based earned value
Author 
Solomon, Paul J., 1942- Young, Ralph Rowland.
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IEEE Xplore http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5989460
IEEE Xplore http://ieeexplore.ieee.org/servlet/opac?bknumber=5989460
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731. 
Cover image for Systems engineering a 21st century systems methodology
Systems engineering a 21st century systems methodology
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Hitchins, Derek K. Wiley InterScience (Online service)
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John Wiley http://dx.doi.org/10.1002/9780470518762
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732. 
Cover image for Systems engineering with SysML/UML modeling, analysis, design
Systems engineering with SysML/UML modeling, analysis, design
Author 
Weilkiens, Tim.
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ONLINE(313039.1)
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Knovel http://app.knovel.com/hotlink/toc/id:kpSESMLUM6/systems-engineering-with
Knovel http://app.knovel.com/web/toc.v/cid:kpSESMLUM6
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