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1. 
Cover image for Logic synthesis for FPGA-based mealy finite state machines : structural decomposition in logic design
Logic synthesis for FPGA-based mealy finite state machines : structural decomposition in logic design
Author 
Barkalov, Alexander, author.
Preferred Shelf Number 
TK7868 .L6
Electronic Access 
Taylor & Francis https://www.taylorfrancis.com/books/9781003536734
OCLC metadata license agreement http://www.oclc.org/content/dam/oclc/forms/terms/vbrl-201703.pdf
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Cover image for Software Defined Chips Volume II
Software Defined Chips Volume II
Author 
Liu, Leibo. author. Wei, Shaojun. author. Zhu, Jianfeng. author. Deng, Chenchen. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
https://doi.org/10.1007/978-981-19-7636-0
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3. 
Cover image for Lectures on digital design principles
Lectures on digital design principles
Author 
Mazumder, Pinaki, author. Ebong, Idongesit E., author
Preferred Shelf Number 
TK7868 .D5
Electronic Access 
Taylor & Francis https://www.taylorfrancis.com/books/9781003425762
OCLC metadata license agreement http://www.oclc.org/content/dam/oclc/forms/terms/vbrl-201703.pdf
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Cover image for Digital Design from the VLSI Perspective Concepts for VLSI Beginners
Digital Design from the VLSI Perspective Concepts for VLSI Beginners
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Taraate, Vaibbhav. author. SpringerLink (Online service)
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ONLINE
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https://doi.org/10.1007/978-981-19-4652-3
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5. 
Cover image for Fundamentals of Modern Electric Circuit Analysis and Filter Synthesis A Transfer Function Approach
Fundamentals of Modern Electric Circuit Analysis and Filter Synthesis A Transfer Function Approach
Author 
Izadian, Afshin. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-031-21908-5
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6. 
Cover image for High Performance Computing 34th International Conference, ISC High Performance 2019, Frankfurt/Main, Germany, June 16–20, 2019, Proceedings
High Performance Computing 34th International Conference, ISC High Performance 2019, Frankfurt/Main, Germany, June 16–20, 2019, Proceedings
Author 
Weiland, Michèle. editor. (orcid)0000-0003-4713-3073 Juckeland, Guido. editor. (orcid)0000-0002-9935-4428 Trinitis, Carsten. editor. (orcid)0000-0002-6750-3652 Sadayappan, Ponnuswamy. editor. (orcid)0000-0002-4737-2034 SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-20656-7
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Cover image for Biomimetic and Biohybrid Systems 8th International Conference, Living Machines 2019, Nara, Japan, July 9–12, 2019, Proceedings
Biomimetic and Biohybrid Systems 8th International Conference, Living Machines 2019, Nara, Japan, July 9–12, 2019, Proceedings
Author 
Martinez-Hernandez, Uriel. editor. (orcid)0000-0002-9922-7912 Vouloutsi, Vasiliki. editor. (orcid)0000-0001-6425-1026 Mura, Anna. editor. Mangan, Michael. editor. (orcid)0000-0002-0293-8874 Asada, Minoru. editor.
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https://doi.org/10.1007/978-3-030-24741-6
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8. 
Cover image for Euro-Par 2019: Parallel Processing 25th International Conference on Parallel and Distributed Computing, Göttingen, Germany, August 26–30, 2019, Proceedings
Euro-Par 2019: Parallel Processing 25th International Conference on Parallel and Distributed Computing, Göttingen, Germany, August 26–30, 2019, Proceedings
Author 
Yahyapour, Ramin. editor. (orcid)0000-0002-9057-4395 SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-29400-7
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9. 
Cover image for High-Performance Computing Applications in Numerical Simulation and Edge Computing ACM ICS 2018 International Workshops, HPCMS and HiDEC, Beijing, China, June 12, 2018, Revised Selected Papers
High-Performance Computing Applications in Numerical Simulation and Edge Computing ACM ICS 2018 International Workshops, HPCMS and HiDEC, Beijing, China, June 12, 2018, Revised Selected Papers
Author 
Hu, Changjun. editor. Yang, Wen. editor. Jiang, Congfeng. editor. Dai, Dong. editor. SpringerLink (Online service)
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https://doi.org/10.1007/978-981-32-9987-0
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10. 
Cover image for Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog
Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog
Author 
Taraate, Vaibbhav. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-981-10-8776-9
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11. 
Cover image for Introduction to Logic Circuits & Logic Design with VHDL
Introduction to Logic Circuits & Logic Design with VHDL
Author 
LaMeres, Brock J. author. SpringerLink (Online service)
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https://doi.org/10.1007/978-3-030-12489-2
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12. 
Cover image for Euro-Par 2018: Parallel Processing Workshops Euro-Par 2018 International Workshops, Turin, Italy, August 27-28, 2018, Revised Selected Papers
Euro-Par 2018: Parallel Processing Workshops Euro-Par 2018 International Workshops, Turin, Italy, August 27-28, 2018, Revised Selected Papers
Author 
Mencagli, Gabriele. editor. B. Heras, Dora. editor. Cardellini, Valeria. editor. Casalicchio, Emiliano. editor. Jeannot, Emmanuel. editor.
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https://doi.org/10.1007/978-3-030-10549-5
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