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1. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers
Author 
Ayala, José L. editor. Shang, Delong. editor. Yakovlev, Alex. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE(334136.1)
Electronic Access 
http://dx.doi.org/10.1007/978-3-642-36157-9
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2. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers
Author 
Leuken, René. editor. Sicard, Gilles. editor. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-3-642-17752-1
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3. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings
Author 
Ayala, José L. editor. García-Cámara, Braulio. editor. Prieto, Manuel. editor. Ruggiero, Martino. editor. Sicard, Gilles. editor.
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-3-642-24154-3
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4. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers
Author 
Monteiro, José. editor. Leuken, René. editor. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-3-642-11802-9
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5. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers
Author 
Svensson, Lars. editor. Monteiro, José. editor. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-3-540-95948-9
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6. 
Cover image for Electronics System Design Techniques for Safety Critical Applications
Electronics System Design Techniques for Safety Critical Applications
Author 
Sterpone, Luca. author. SpringerLink (Online service)
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ONLINE
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http://dx.doi.org/10.1007/978-1-4020-8979-4
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7. 
Cover image for Introduction to Embedded System Design Using Field Programmable Gate Arrays
Introduction to Embedded System Design Using Field Programmable Gate Arrays
Author 
Dubey, Rahul. author. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/978-1-84882-016-6
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8. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedings
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedings
Author 
Azémard, Nadine. editor. Svensson, Lars. editor. SpringerLink (Online service)
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ONLINE
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http://dx.doi.org/10.1007/978-3-540-74442-9
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9. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings
Author 
Vounckx, Johan. editor. Azemard, Nadine. editor. Maurine, Philippe. editor. SpringerLink (Online service)
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ONLINE
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http://dx.doi.org/10.1007/11847083
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10. 
Cover image for Logically determined design clockless system design with NULL convention logic
Logically determined design clockless system design with NULL convention logic
Author 
Fant, Karl M.
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Available by subscription from Safari Books Online
John Wiley http://dx.doi.org/10.1002/0471702897
MyiLibrary, Table of contents http://www.myilibrary.com?id=25243&ref=toc
Volltext http://proquest.tech.safaribooksonline.de/9780471684787
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11. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings
Author 
Paliouras, Vassilis. editor. Vounckx, Johan. editor. Verkest, Diederik. editor. SpringerLink (Online service)
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ONLINE
Electronic Access 
http://dx.doi.org/10.1007/11556930
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