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1. 
Cover image for DSP processor fundamentals architectures and features
DSP processor fundamentals architectures and features
Author 
Lapsley, Phil, 1965-
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ONLINE
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IEEE Xplore http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5266186
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Cover image for Applied Reconfigurable Computing. Architectures, Tools, and Applications 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023, Proceedings
Applied Reconfigurable Computing. Architectures, Tools, and Applications 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023, Proceedings
Author 
Palumbo, Francesca. editor. Keramidas, Georgios. editor. Voros, Nikolaos. editor. Diniz, Pedro C. editor. SpringerLink (Online service)
Preferred Shelf Number 
XX(521144.1)
Electronic Access 
https://doi.org/10.1007/978-3-031-42921-7
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3. 
Cover image for Applied Reconfigurable Computing 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings
Applied Reconfigurable Computing 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings
Author 
Sano, Kentaro. editor. Soudris, Dimitrios. editor. Hübner, Michael. editor. Diniz, Pedro C. editor. SpringerLink (Online service)
Preferred Shelf Number 
XX(519004.1)
Electronic Access 
https://doi.org/10.1007/978-3-319-16214-0
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4. 
Cover image for Cryptography and Information Security in the Balkans First International Conference, BalkanCryptSec 2014, Istanbul, Turkey, October 16-17, 2014, Revised Selected Papers
Cryptography and Information Security in the Balkans First International Conference, BalkanCryptSec 2014, Istanbul, Turkey, October 16-17, 2014, Revised Selected Papers
Author 
Ors, Berna. editor. Preneel, Bart. editor. SpringerLink (Online service)
Preferred Shelf Number 
XX(518872.1)
Electronic Access 
https://doi.org/10.1007/978-3-319-21356-9
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5. 
Cover image for Multicore technology : architecture, reconfiguration, and modeling
Multicore technology : architecture, reconfiguration, and modeling
Author 
Samgwine, Stephen J., editor. Qadri, Muhammad Yasir, editor.
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Distributed by publisher. Purchase or institutional license may be required for access.
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6. 
Cover image for Partial Reconfiguration on FPGAs Architectures, Tools and Applications
Partial Reconfiguration on FPGAs Architectures, Tools and Applications
Author 
Koch, Dirk. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE(331261.1)
Electronic Access 
http://dx.doi.org/10.1007/978-1-4614-1225-0
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7. 
Cover image for System-Level Validation High-Level Modeling and Directed Test Generation Techniques
System-Level Validation High-Level Modeling and Directed Test Generation Techniques
Author 
Chen, Mingsong. author. Qin, Xiaoke. author. Koo, Heon-Mo. author. Mishra, Prabhat. author. SpringerLink (Online service)
Preferred Shelf Number 
ONLINE(331265.1)
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http://dx.doi.org/10.1007/978-1-4614-1359-2
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8. 
Cover image for Embedded Systems Design with FPGAs
Embedded Systems Design with FPGAs
Author 
Athanas, Peter. editor. Pnevmatikatos, Dionisios. editor. Sklavos, Nicolas. editor. SpringerLink (Online service)
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ONLINE(331266.1)
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http://dx.doi.org/10.1007/978-1-4614-1362-2
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9. 
Cover image for High-Performance Computing Using FPGAs
High-Performance Computing Using FPGAs
Author 
Vanderbauwhede, Wim. editor. Benkrid, Khaled. editor. SpringerLink (Online service)
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ONLINE(331283.1)
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http://dx.doi.org/10.1007/978-1-4614-1791-0
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10. 
Cover image for Self-Organization in Embedded Real-Time Systems
Self-Organization in Embedded Real-Time Systems
Author 
Higuera-Toledano, M. Teresa. editor. Brinkschulte, Uwe. editor. Rettberg, Achim. editor. SpringerLink (Online service)
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ONLINE(331293.1)
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http://dx.doi.org/10.1007/978-1-4614-1969-3
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11. 
Cover image for UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs
UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs
Author 
Daněk, Martin. author. Kafka, Leoš. author. Kohout, Lukáš. author. Sýkora, Jaroslav. author. Bartosinski, Roman. author.
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ONLINE(331311.1)
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http://dx.doi.org/10.1007/978-1-4614-2410-9
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12. 
Cover image for Constraining Designs for Synthesis and Timing Analysis A Practical Guide to Synopsys Design Constraints (SDC)
Constraining Designs for Synthesis and Timing Analysis A Practical Guide to Synopsys Design Constraints (SDC)
Author 
Gangadharan, Sridhar. author. Churiwala, Sanjay. author. SpringerLink (Online service)
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ONLINE(331327.1)
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http://dx.doi.org/10.1007/978-1-4614-3269-2
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