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SirsiDynix Enterprise https://katalog.hacettepe.edu.tr/client/en_US/default/default/qf$003dITYPE$002509Material$002bType$0025091$00253AE-KITAP$002509E-Book$0026qf$003dLOCATION$002509Shelf$002bLocation$0025091$00253AELEKKUTUPH$002509Electronic$002bLibrary$0026qf$003dPUBDATE$002509Publication$002bDate$0025092006$0025092006$0026qf$003dSUBJECT$002509Subject$002509Computer$002baided$002bdesign.$002509Computer$002baided$002bdesign.$0026qf$003dSUBJECT$002509Subject$002509Systems$002bengineering.$002509Systems$002bengineering.$0026ps$003d300$0026isd$003dtrue? 2024-08-27T20:16:10Z Abstraction Refinement for Large Scale Model Checking ent://SD_ILS/0/SD_ILS:166047 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Wang, Chao. author.&#160;Hachtel, Gary D. author.&#160;Somenzi, Fabio. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/0-387-34600-7">http://dx.doi.org/10.1007/0-387-34600-7</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> The Core Test Wrapper Handbook Rationale and Application of IEEE Std. 1500&trade; ent://SD_ILS/0/SD_ILS:166049 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Silva, Francisco. author.&#160;McLaurin, Teresa. author.&#160;Waayers, Tom. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/0-387-34609-0">http://dx.doi.org/10.1007/0-387-34609-0</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Layoutsynthese elektronischer Schaltungen &mdash; Grundlegende Algorithmen f&uuml;r die Entwurfsautomatisierung ent://SD_ILS/0/SD_ILS:182190 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Lienig, Jens. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/3-540-29942-4">http://dx.doi.org/10.1007/3-540-29942-4</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Semiconductor Modeling For Simulating Signal, Power, and Electromagnetic Integrity ent://SD_ILS/0/SD_ILS:165020 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Leventhal, Roy G. author.&#160;Green, Lynne. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/b104647">http://dx.doi.org/10.1007/b104647</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Leakage in Nanometer CMOS Technologies ent://SD_ILS/0/SD_ILS:165474 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Narendra, Siva G. author.&#160;Chandrakasan, Anantha. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/0-387-28133-9">http://dx.doi.org/10.1007/0-387-28133-9</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Scalable Hardware Verification with Symbolic Simulation ent://SD_ILS/0/SD_ILS:165683 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Bertacco, Valeria. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/0-387-29906-8">http://dx.doi.org/10.1007/0-387-29906-8</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Embedded System Design ent://SD_ILS/0/SD_ILS:165694 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Marwedel, Peter. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/0-387-30087-2">http://dx.doi.org/10.1007/0-387-30087-2</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Hardware Verification with C++ A Practitioner&rsquo;s Handbook ent://SD_ILS/0/SD_ILS:166141 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Mintz, Mike. author.&#160;Ekendahl, Robert. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-0-387-36254-0">http://dx.doi.org/10.1007/978-0-387-36254-0</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> SystemVerilog for Design A Guide to Using SystemVerilog for Hardware Design and Modeling ent://SD_ILS/0/SD_ILS:166152 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Sutherland, Stuart. author.&#160;Davidmann, Simon. author.&#160;Flake, Peter. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/0-387-36495-1">http://dx.doi.org/10.1007/0-387-36495-1</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Electromagnetic Compatibility of Integrated Circuits Techniques for low emission and susceptibility ent://SD_ILS/0/SD_ILS:165289 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Ben Dhia, Sonia. editor.&#160;Ramdani, Mohamed. editor.&#160;Sicard, Etienne. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/b137864">http://dx.doi.org/10.1007/b137864</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Systemverilog for Verification A Guide to Learning the Testbench Language Features ent://SD_ILS/0/SD_ILS:165314 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Spear, Chris. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/b138536">http://dx.doi.org/10.1007/b138536</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Thermal and Power Management of Integrated Circuits ent://SD_ILS/0/SD_ILS:165670 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Vassighi, Arman. author.&#160;Sachdev, Manoj. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/0-387-29749-9">http://dx.doi.org/10.1007/0-387-29749-9</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Reuse-Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits ent://SD_ILS/0/SD_ILS:169386 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;CASTRO-L&Oacute;PEZ, R. author.&#160;FERN&Aacute;NDEZ, F.V. author.&#160;GUERRA-VINUESA, O. author.&#160;RODR&Iacute;GUEZ-V&Aacute;ZQUEZ, &Aacute;. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-1-4020-5139-5">http://dx.doi.org/10.1007/978-1-4020-5139-5</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Verification Methodology Manual for SystemVerilog ent://SD_ILS/0/SD_ILS:165150 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Bergeron, Janick. author.&#160;Cerny, Eduard. author.&#160;Hunter, Alan. author.&#160;Nightingale, Andrew. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/b135575">http://dx.doi.org/10.1007/b135575</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Rapid Prototyping of Digital Systems ent://SD_ILS/0/SD_ILS:165587 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Hamblen, James O. author.&#160;Hall, Tyson S. author.&#160;Furman, Michael D. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/0-387-28965-8">http://dx.doi.org/10.1007/0-387-28965-8</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Interconnect Noise Optimization in Nanometer Technologies ent://SD_ILS/0/SD_ILS:165637 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Elgamel, Mohamed A. author.&#160;Bayoumi, Magdy A. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/0-387-29366-3">http://dx.doi.org/10.1007/0-387-29366-3</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Writing Testbenches using System Verilog ent://SD_ILS/0/SD_ILS:165809 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Bergeron, Janick. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/0-387-31275-7">http://dx.doi.org/10.1007/0-387-31275-7</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Constraint-Based Verification ent://SD_ILS/0/SD_ILS:165761 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Yuan, Jun. author.&#160;Pixley, Carl. author.&#160;Aziz, Adnan. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/0-387-30784-2">http://dx.doi.org/10.1007/0-387-30784-2</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> A Practical Introduction to PSL ent://SD_ILS/0/SD_ILS:166138 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Eisner, Cindy. author.&#160;Fisman, Dana. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-0-387-36123-9">http://dx.doi.org/10.1007/978-0-387-36123-9</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> A Roadmap for Formal Property Verification ent://SD_ILS/0/SD_ILS:169271 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;DasGupta, Pallab. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-1-4020-4758-9">http://dx.doi.org/10.1007/978-1-4020-4758-9</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms ent://SD_ILS/0/SD_ILS:169289 2024-08-27T20:16:10Z 2024-08-27T20:16:10Z Author&#160;Kogel, Tim. author.&#160;Leupers, Rainer. author.&#160;Meyr, Heinrich. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a 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