Search Results for -- UYGARLIK, ORTA&Ccedil;A&#286;, EDEB&#304;YATTA. - Narrowed by: Logic design. - Memory management (Computer science). SirsiDynix Enterprise https://katalog.hacettepe.edu.tr/client/en_US/default/default/qu$003d--$002bUYGARLIK$00252C$002bORTA$0025C3$002587A$0025C4$00259E$00252C$002bEDEB$0025C4$0025B0YATTA.$0026qf$003dSUBJECT$002509Subject$002509Logic$002bdesign.$002509Logic$002bdesign.$0026qf$003dSUBJECT$002509Subject$002509Memory$002bmanagement$002b$002528Computer$002bscience$002529.$002509Memory$002bmanagement$002b$002528Computer$002bscience$002529.$0026ic$003dtrue$0026te$003dILS$0026ps$003d300?dt=list 2024-08-11T21:51:41Z Computer Engineering and Technology 16th National Conference, NCCET 2012, Shanghai, China, August 17-19, 2012, Revised Selected Papers ent://SD_ILS/0/SD_ILS:334080 2024-08-11T21:51:41Z 2024-08-11T21:51:41Z Author&#160;Xu, Weixia. editor.&#160;Xiao, Liquan. editor.&#160;Lu, Pingjing. editor.&#160;Li, Jinwen. editor.&#160;Zhang, Chengyi. editor.<br/>Preferred Shelf Number&#160;ONLINE(334080.1)<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-3-642-35898-2">http://dx.doi.org/10.1007/978-3-642-35898-2</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Computer Engineering and Technology 17th CCF Conference, NCCET 2013, Xining, China, July 20-22, 2013. Revised Selected Papers ent://SD_ILS/0/SD_ILS:335131 2024-08-11T21:51:41Z 2024-08-11T21:51:41Z Author&#160;Xu, Weixia. editor.&#160;Xiao, Liquan. editor.&#160;Zhang, Chengyi. editor.&#160;Li, Jinwen. editor.&#160;Yu, Liyan. editor.<br/>Preferred Shelf Number&#160;ONLINE(335131.1)<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-3-642-41635-4">http://dx.doi.org/10.1007/978-3-642-41635-4</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers ent://SD_ILS/0/SD_ILS:191802 2024-08-11T21:51:41Z 2024-08-11T21:51:41Z Author&#160;Monteiro, Jos&eacute;. editor.&#160;Leuken, Ren&eacute;. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-3-642-11802-9">http://dx.doi.org/10.1007/978-3-642-11802-9</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Computer Performance Evaluation and Benchmarking SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009. Proceedings ent://SD_ILS/0/SD_ILS:189510 2024-08-11T21:51:41Z 2024-08-11T21:51:41Z Author&#160;Kaeli, David. editor.&#160;Sachs, Kai. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-3-540-93799-9">http://dx.doi.org/10.1007/978-3-540-93799-9</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers ent://SD_ILS/0/SD_ILS:189565 2024-08-11T21:51:41Z 2024-08-11T21:51:41Z Author&#160;Svensson, Lars. editor.&#160;Monteiro, Jos&eacute;. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-3-540-95948-9">http://dx.doi.org/10.1007/978-3-540-95948-9</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedings ent://SD_ILS/0/SD_ILS:187155 2024-08-11T21:51:41Z 2024-08-11T21:51:41Z Author&#160;Az&eacute;mard, Nadine. editor.&#160;Svensson, Lars. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-3-540-74442-9">http://dx.doi.org/10.1007/978-3-540-74442-9</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings ent://SD_ILS/0/SD_ILS:184718 2024-08-11T21:51:41Z 2024-08-11T21:51:41Z Author&#160;Vounckx, Johan. editor.&#160;Azemard, Nadine. editor.&#160;Maurine, Philippe. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/11847083">http://dx.doi.org/10.1007/11847083</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/>