Search Results for Art and architecture. - Narrowed by: Processor Architectures. SirsiDynix Enterprise https://katalog.hacettepe.edu.tr/client/en_US/default/default/qu$003dArt$002band$002barchitecture.$0026qf$003dSUBJECT$002509Subject$002509Processor$002bArchitectures.$002509Processor$002bArchitectures.$0026ps$003d300?dt=list 2026-03-26T19:55:41Z High Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture ent://SD_ILS/0/SD_ILS:604592 2026-03-26T19:55:41Z 2026-03-26T19:55:41Z Author&#160;Yue, Jinshan. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="https://doi.org/10.1007/978-981-97-3477-1">https://doi.org/10.1007/978-981-97-3477-1</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Fundamentals of IP and SoC Security Design, Verification, and Debug ent://SD_ILS/0/SD_ILS:614582 2026-03-26T19:55:41Z 2026-03-26T19:55:41Z Author&#160;Bhunia, Swarup. editor.&#160;Ray, Sandip. editor.&#160;Sur-Kolay, Susmita. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="https://doi.org/10.1007/978-3-319-50057-7">https://doi.org/10.1007/978-3-319-50057-7</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Emerging Technology and Architecture for Big-data Analytics ent://SD_ILS/0/SD_ILS:615642 2026-03-26T19:55:41Z 2026-03-26T19:55:41Z Author&#160;Chattopadhyay, Anupam. editor. (orcid)0000-0002-8818-6983&#160;Chang, Chip Hong. editor.&#160;Yu, Hao. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="https://doi.org/10.1007/978-3-319-54840-1">https://doi.org/10.1007/978-3-319-54840-1</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Techniques for Building Timing-Predictable Embedded Systems ent://SD_ILS/0/SD_ILS:611833 2026-03-26T19:55:41Z 2026-03-26T19:55:41Z Author&#160;Guan, Nan. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="https://doi.org/10.1007/978-3-319-27198-9">https://doi.org/10.1007/978-3-319-27198-9</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Memory Controllers for Mixed-Time-Criticality Systems Architectures, Methodologies and Trade-offs ent://SD_ILS/0/SD_ILS:613609 2026-03-26T19:55:41Z 2026-03-26T19:55:41Z Author&#160;Goossens, Sven. author.&#160;Chandrasekar, Karthik. author.&#160;Akesson, Benny. author.&#160;Goossens, Kees. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="https://doi.org/10.1007/978-3-319-32094-6">https://doi.org/10.1007/978-3-319-32094-6</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/>