Search Results for Computer science. - Narrowed by: English - Logic design. - Systems engineering.
SirsiDynix Enterprise
https://katalog.hacettepe.edu.tr/client/en_US/default/default/qu$003dComputer$002bscience.$0026qf$003dLANGUAGE$002509Language$002509ENG$002509English$0026qf$003dSUBJECT$002509Subject$002509Logic$002bdesign.$002509Logic$002bdesign.$0026qf$003dSUBJECT$002509Subject$002509Systems$002bengineering.$002509Systems$002bengineering.$0026te$003dILS$0026ps$003d300$0026isd$003dtrue?
2024-09-06T07:59:17Z
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers
ent://SD_ILS/0/SD_ILS:189565
2024-09-06T07:59:17Z
2024-09-06T07:59:17Z
Author Svensson, Lars. editor. Monteiro, José. editor. SpringerLink (Online service)<br/>Preferred Shelf Number ONLINE<br/>Electronic Access <a href="http://dx.doi.org/10.1007/978-3-540-95948-9">http://dx.doi.org/10.1007/978-3-540-95948-9</a><br/>Format: Electronic Resources<br/>Availability Online Library~1<br/>
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedings
ent://SD_ILS/0/SD_ILS:187155
2024-09-06T07:59:17Z
2024-09-06T07:59:17Z
Author Azémard, Nadine. editor. Svensson, Lars. editor. SpringerLink (Online service)<br/>Preferred Shelf Number ONLINE<br/>Electronic Access <a href="http://dx.doi.org/10.1007/978-3-540-74442-9">http://dx.doi.org/10.1007/978-3-540-74442-9</a><br/>Format: Electronic Resources<br/>Availability Online Library~1<br/>
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings
ent://SD_ILS/0/SD_ILS:184718
2024-09-06T07:59:17Z
2024-09-06T07:59:17Z
Author Vounckx, Johan. editor. Azemard, Nadine. editor. Maurine, Philippe. editor. SpringerLink (Online service)<br/>Preferred Shelf Number ONLINE<br/>Electronic Access <a href="http://dx.doi.org/10.1007/11847083">http://dx.doi.org/10.1007/11847083</a><br/>Format: Electronic Resources<br/>Availability Online Library~1<br/>
ASIC/SoC Functional Design Verification A Comprehensive Guide to Technologies and Methodologies
ent://SD_ILS/0/SD_ILS:401372
2024-09-06T07:59:17Z
2024-09-06T07:59:17Z
Author Mehta, Ashok B. author. SpringerLink (Online service)<br/>Preferred Shelf Number ONLINE<br/>Electronic Access <a href="https://doi.org/10.1007/978-3-319-59418-7">https://doi.org/10.1007/978-3-319-59418-7</a><br/>Format: Electronic Resources<br/>Availability Online Library~1<br/>
Reliable and Energy Efficient Streaming Multiprocessor Systems
ent://SD_ILS/0/SD_ILS:401431
2024-09-06T07:59:17Z
2024-09-06T07:59:17Z
Author Das, Anup Kumar. author. Kumar, Akash. author. Veeravalli, Bharadwaj. author. Catthoor, Francky. author. SpringerLink (Online service)<br/>Preferred Shelf Number ONLINE<br/>Electronic Access <a href="https://doi.org/10.1007/978-3-319-69374-3">https://doi.org/10.1007/978-3-319-69374-3</a><br/>Format: Electronic Resources<br/>Availability Online Library~1<br/>
Design of FPGA-Based Computing Systems with OpenCL
ent://SD_ILS/0/SD_ILS:401920
2024-09-06T07:59:17Z
2024-09-06T07:59:17Z
Author Waidyasooriya, Hasitha Muthumala. author. Hariyama, Masanori. author. Uchiyama, Kunio. author. SpringerLink (Online service)<br/>Preferred Shelf Number ONLINE<br/>Electronic Access <a href="https://doi.org/10.1007/978-3-319-68161-0">https://doi.org/10.1007/978-3-319-68161-0</a><br/>Format: Electronic Resources<br/>Availability Online Library~1<br/>
Simulation and Optimization of Digital Circuits Considering and Mitigating Destabilizing Factors
ent://SD_ILS/0/SD_ILS:399090
2024-09-06T07:59:17Z
2024-09-06T07:59:17Z
Author Melikyan, Vazgen. author. SpringerLink (Online service)<br/>Preferred Shelf Number ONLINE<br/>Electronic Access <a href="https://doi.org/10.1007/978-3-319-71637-4">https://doi.org/10.1007/978-3-319-71637-4</a><br/>Format: Electronic Resources<br/>Availability Online Library~1<br/>
Design, Analysis and Test of Logic Circuits Under Uncertainty
ent://SD_ILS/0/SD_ILS:335669
2024-09-06T07:59:17Z
2024-09-06T07:59:17Z
Author Krishnaswamy, Smita. author. Markov, Igor L. author. Hayes, John P. author. SpringerLink (Online service)<br/>Preferred Shelf Number ONLINE(335669.1)<br/>Electronic Access <a href="http://dx.doi.org/10.1007/978-90-481-9644-9">http://dx.doi.org/10.1007/978-90-481-9644-9</a><br/>Format: Electronic Resources<br/>Availability Online Library~1<br/>
Logic Functions and Equations Examples and Exercises
ent://SD_ILS/0/SD_ILS:170583
2024-09-06T07:59:17Z
2024-09-06T07:59:17Z
Author Steinbach, Bernd. author. Posthoff, Christian. author. SpringerLink (Online service)<br/>Preferred Shelf Number ONLINE<br/>Electronic Access <a href="http://dx.doi.org/10.1007/978-1-4020-9595-5">http://dx.doi.org/10.1007/978-1-4020-9595-5</a><br/>Format: Electronic Resources<br/>Availability Online Library~1<br/>
High-Level Synthesis From Algorithm to Digital Circuit
ent://SD_ILS/0/SD_ILS:170235
2024-09-06T07:59:17Z
2024-09-06T07:59:17Z
Author Coussy, Philippe. editor. Morawiec, Adam. editor. SpringerLink (Online service)<br/>Preferred Shelf Number ONLINE<br/>Electronic Access <a href="http://dx.doi.org/10.1007/978-1-4020-8588-8">http://dx.doi.org/10.1007/978-1-4020-8588-8</a><br/>Format: Electronic Resources<br/>Availability Online Library~1<br/>
A Roadmap for Formal Property Verification
ent://SD_ILS/0/SD_ILS:169271
2024-09-06T07:59:17Z
2024-09-06T07:59:17Z
Author DasGupta, Pallab. author. SpringerLink (Online service)<br/>Preferred Shelf Number ONLINE<br/>Electronic Access <a href="http://dx.doi.org/10.1007/978-1-4020-4758-9">http://dx.doi.org/10.1007/978-1-4020-4758-9</a><br/>Format: Electronic Resources<br/>Availability Online Library~1<br/>