Search Results for Field programmable gate arrays - Narrowed by: Electronic circuits. SirsiDynix Enterprise https://katalog.hacettepe.edu.tr/client/en_US/default/default/qu$003dField$002bprogrammable$002bgate$002barrays$0026qf$003dSUBJECT$002509Konu$002509Electronic$002bcircuits.$002509Electronic$002bcircuits.$0026ic$003dtrue$0026ps$003d300? 2026-05-11T18:25:29Z Digital Signal Processing with Field Programmable Gate Arrays ent://SD_ILS/0/SD_ILS:487323 2026-05-11T18:25:29Z 2026-05-11T18:25:29Z Author&#160;Meyer-Baese, Uwe. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="https://doi.org/10.1007/978-3-642-45309-0">https://doi.org/10.1007/978-3-642-45309-0</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> High-Speed Decoders for Polar Codes ent://SD_ILS/0/SD_ILS:615873 2026-05-11T18:25:29Z 2026-05-11T18:25:29Z Author&#160;Giard, Pascal. author.&#160;Thibeault, Claude. author.&#160;Gross, Warren J. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="https://doi.org/10.1007/978-3-319-59782-9">https://doi.org/10.1007/978-3-319-59782-9</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Separation Logic for High-level Synthesis ent://SD_ILS/0/SD_ILS:614385 2026-05-11T18:25:29Z 2026-05-11T18:25:29Z Author&#160;Winterstein, Felix. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="https://doi.org/10.1007/978-3-319-53222-6">https://doi.org/10.1007/978-3-319-53222-6</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> High Performance Integer Arithmetic Circuit Design on FPGA Architecture, Implementation and Design Automation ent://SD_ILS/0/SD_ILS:612605 2026-05-11T18:25:29Z 2026-05-11T18:25:29Z Author&#160;Palchaudhuri, Ayan. author.&#160;Chakraborty, Rajat Subhra. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="https://doi.org/10.1007/978-81-322-2520-1">https://doi.org/10.1007/978-81-322-2520-1</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Logic Synthesis for FPGA-Based Finite State Machines ent://SD_ILS/0/SD_ILS:614362 2026-05-11T18:25:29Z 2026-05-11T18:25:29Z Author&#160;Barkalov, Alexander. author.&#160;Titarenko, Larysa. author.&#160;Kolopienczyk, Malgorzata. author.&#160;Mielcarek, Kamil. author.&#160;Bazydlo, Grzegorz. author.<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="https://doi.org/10.1007/978-3-319-24202-6">https://doi.org/10.1007/978-3-319-24202-6</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Fuzzy Logic Type 1 and Type 2 Based on LabVIEW&trade; FPGA ent://SD_ILS/0/SD_ILS:612885 2026-05-11T18:25:29Z 2026-05-11T18:25:29Z Author&#160;Ponce-Cruz, Pedro. author.&#160;Molina, Arturo. author.&#160;MacCleery, Brian. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="https://doi.org/10.1007/978-3-319-26656-5">https://doi.org/10.1007/978-3-319-26656-5</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Three-Dimensional Design Methodologies for Tree-based FPGA Architecture ent://SD_ILS/0/SD_ILS:529226 2026-05-11T18:25:29Z 2026-05-11T18:25:29Z Author&#160;Pangracious, Vinod. author.&#160;Marrakchi, Zied. author.&#160;Mehrez, Habib. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="https://doi.org/10.1007/978-3-319-19174-4">https://doi.org/10.1007/978-3-319-19174-4</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/>