Search Results for Logic design - Narrowed by: Ayala, Jos&eacute; L. editor. - SpringerLink (Online service) SirsiDynix Enterprise https://katalog.hacettepe.edu.tr/client/en_US/default/default/qu$003dLogic$002bdesign$0026qf$003dAUTHOR$002509Author$002509Ayala$00252C$002bJos$0025C3$0025A9$002bL.$002beditor.$002509Ayala$00252C$002bJos$0025C3$0025A9$002bL.$002beditor.$0026qf$003dAUTHOR$002509Author$002509SpringerLink$002b$002528Online$002bservice$002529$002509SpringerLink$002b$002528Online$002bservice$002529$0026ic$003dtrue$0026te$003dILS$0026ps$003d300$0026isd$003dtrue? 2024-08-21T23:01:08Z Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers ent://SD_ILS/0/SD_ILS:334136 2024-08-21T23:01:08Z 2024-08-21T23:01:08Z Author&#160;Ayala, Jos&eacute; L. editor.&#160;Shang, Delong. editor.&#160;Yakovlev, Alex. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE(334136.1)<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-3-642-36157-9">http://dx.doi.org/10.1007/978-3-642-36157-9</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings ent://SD_ILS/0/SD_ILS:195562 2024-08-21T23:01:08Z 2024-08-21T23:01:08Z Author&#160;Ayala, Jos&eacute; L. editor.&#160;Garc&iacute;a-C&aacute;mara, Braulio. editor.&#160;Prieto, Manuel. editor.&#160;Ruggiero, Martino. editor.&#160;Sicard, Gilles. editor.<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-3-642-24154-3">http://dx.doi.org/10.1007/978-3-642-24154-3</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/>