Search Results for Logic. - Narrowed by: Computer aided design. SirsiDynix Enterprise https://katalog.hacettepe.edu.tr/client/en_US/default/default/qu$003dLogic.$0026qf$003dSUBJECT$002509Subject$002509Computer$002baided$002bdesign.$002509Computer$002baided$002bdesign.$0026ic$003dtrue$0026ps$003d300$0026isd$003dtrue?dt=list 2024-11-27T21:36:11Z Memory-Based Logic Synthesis ent://SD_ILS/0/SD_ILS:173066 2024-11-27T21:36:11Z 2024-11-27T21:36:11Z Author&#160;Sasao, Tsutomu. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-1-4419-8104-2">http://dx.doi.org/10.1007/978-1-4419-8104-2</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Advanced Techniques in Logic Synthesis, Optimizations and Applications ent://SD_ILS/0/SD_ILS:172897 2024-11-27T21:36:11Z 2024-11-27T21:36:11Z Author&#160;Gulati, Kanupriya. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-1-4419-7518-8">http://dx.doi.org/10.1007/978-1-4419-7518-8</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> VLSI Physical Design: From Graph Partitioning to Timing Closure ent://SD_ILS/0/SD_ILS:205534 2024-11-27T21:36:11Z 2024-11-27T21:36:11Z Author&#160;Kahng, Andrew B. author.&#160;Lienig, Jens. author.&#160;Markov, Igor L. author.&#160;Hu, Jin. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-90-481-9591-6">http://dx.doi.org/10.1007/978-90-481-9591-6</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Regular Nanofabrics in Emerging Technologies Design and Fabrication Methods for Nanoscale Digital Circuits ent://SD_ILS/0/SD_ILS:205904 2024-11-27T21:36:11Z 2024-11-27T21:36:11Z Author&#160;Ben Jamaa, M. Haykel. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-94-007-0650-7">http://dx.doi.org/10.1007/978-94-007-0650-7</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Introduction to Embedded System Design Using Field Programmable Gate Arrays ent://SD_ILS/0/SD_ILS:175875 2024-11-27T21:36:11Z 2024-11-27T21:36:11Z Author&#160;Dubey, Rahul. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-1-84882-016-6">http://dx.doi.org/10.1007/978-1-84882-016-6</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Functional Design Errors in Digital Circuits Diagnosis, Correction and Repair ent://SD_ILS/0/SD_ILS:170513 2024-11-27T21:36:11Z 2024-11-27T21:36:11Z Author&#160;Chang, Kai-hui. author.&#160;Markov, Igor L. author.&#160;Bertacco, Valeria. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-1-4020-9365-4">http://dx.doi.org/10.1007/978-1-4020-9365-4</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Evolvable Systems: From Biology to Hardware 8th International Conference, ICES 2008, Prague, Czech Republic, September 21-24, 2008. Proceedings ent://SD_ILS/0/SD_ILS:188793 2024-11-27T21:36:11Z 2024-11-27T21:36:11Z Author&#160;Hornby, Gregory S. editor.&#160;Sekanina, Luk&aacute;&scaron;. editor.&#160;Haddow, Pauline C. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-3-540-85857-7">http://dx.doi.org/10.1007/978-3-540-85857-7</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Evolvable Systems: From Biology to Hardware 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007 Proceedings ent://SD_ILS/0/SD_ILS:187218 2024-11-27T21:36:11Z 2024-11-27T21:36:11Z Author&#160;Kang, Lishan. editor.&#160;Liu, Yong. editor.&#160;Zeng, Sanyou. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-3-540-74626-3">http://dx.doi.org/10.1007/978-3-540-74626-3</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Computer Aided Systems Theory &ndash; EUROCAST 2007 11th International Conference on Computer Aided Systems Theory, Las Palmas de Gran Canaria, Spain, February 12-16, 2007, Revised Selected Papers ent://SD_ILS/0/SD_ILS:187522 2024-11-27T21:36:11Z 2024-11-27T21:36:11Z Author&#160;Moreno D&iacute;az, Roberto. editor.&#160;Pichler, Franz. editor.&#160;Quesada Arencibia, Alexis. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-3-540-75867-9">http://dx.doi.org/10.1007/978-3-540-75867-9</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> A Roadmap for Formal Property Verification ent://SD_ILS/0/SD_ILS:169271 2024-11-27T21:36:11Z 2024-11-27T21:36:11Z Author&#160;DasGupta, Pallab. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-1-4020-4758-9">http://dx.doi.org/10.1007/978-1-4020-4758-9</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Layoutsynthese elektronischer Schaltungen &mdash; Grundlegende Algorithmen f&uuml;r die Entwurfsautomatisierung ent://SD_ILS/0/SD_ILS:182190 2024-11-27T21:36:11Z 2024-11-27T21:36:11Z Author&#160;Lienig, Jens. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/3-540-29942-4">http://dx.doi.org/10.1007/3-540-29942-4</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Taxonomies for the Development and Verification of Digital Systems ent://SD_ILS/0/SD_ILS:165002 2024-11-27T21:36:11Z 2024-11-27T21:36:11Z Author&#160;Bailey, Brian. editor.&#160;Martin, Grant. editor.&#160;Anderson, Thomas. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/b104217">http://dx.doi.org/10.1007/b104217</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Computer Aided Systems Theory &ndash; EUROCAST 2005 10th International Conference on Computer Aided Systems Theory, Las Palmas de Gran Canaria, Spain, February 7 &ndash; 11, 2005, Revised Selected Papers ent://SD_ILS/0/SD_ILS:182915 2024-11-27T21:36:11Z 2024-11-27T21:36:11Z Author&#160;Moreno D&iacute;az, Roberto. editor.&#160;Pichler, Franz. editor.&#160;Quesada Arencibia, Alexis. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/11556985">http://dx.doi.org/10.1007/11556985</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings ent://SD_ILS/0/SD_ILS:183143 2024-11-27T21:36:11Z 2024-11-27T21:36:11Z Author&#160;Paliouras, Vassilis. editor.&#160;Vounckx, Johan. editor.&#160;Verkest, Diederik. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/11556930">http://dx.doi.org/10.1007/11556930</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Evolvable Systems: From Biology to Hardware 6th International Conference, ICES 2005, Sitges, Spain, September 12-14, 2005. Proceedings ent://SD_ILS/0/SD_ILS:181842 2024-11-27T21:36:11Z 2024-11-27T21:36:11Z Author&#160;Moreno, J. Manuel. editor.&#160;Madrenas, Jordi. editor.&#160;Cosp, Jordi. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/11549703">http://dx.doi.org/10.1007/11549703</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> New Algorithms, Architectures and Applications for Reconfigurable Computing ent://SD_ILS/0/SD_ILS:168817 2024-11-27T21:36:11Z 2024-11-27T21:36:11Z Author&#160;Lysaght, Patrick. editor.&#160;Rosenstiel, Wolfgang. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/1-4020-3128-9">http://dx.doi.org/10.1007/1-4020-3128-9</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Correct Hardware Design and Verification Methods 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbr&uuml;cken, Germany, October 3-6, 2005. Proceedings ent://SD_ILS/0/SD_ILS:183095 2024-11-27T21:36:11Z 2024-11-27T21:36:11Z Author&#160;Borrione, Dominique. editor.&#160;Paul, Wolfgang. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/11560548">http://dx.doi.org/10.1007/11560548</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/>