Search Results for Processor Architectures. - Narrowed by: Electronics. SirsiDynix Enterprise https://katalog.hacettepe.edu.tr/client/en_US/default/default/qu$003dProcessor$002bArchitectures.$0026qf$003dSUBJECT$002509Subject$002509Electronics.$002509Electronics.$0026ps$003d300$0026isd$003dtrue?dt=list 2025-04-27T19:34:14Z Emerging Computing: From Devices to Systems Looking Beyond Moore and Von Neumann ent://SD_ILS/0/SD_ILS:527384 2025-04-27T19:34:14Z 2025-04-27T19:34:14Z Author&#160;Aly, Mohamed M. Sabry. editor.&#160;Chattopadhyay, Anupam. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="https://doi.org/10.1007/978-981-16-7487-7">https://doi.org/10.1007/978-981-16-7487-7</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Software Defined Chips Volume II ent://SD_ILS/0/SD_ILS:527085 2025-04-27T19:34:14Z 2025-04-27T19:34:14Z Author&#160;Liu, Leibo. author.&#160;Wei, Shaojun. author.&#160;Zhu, Jianfeng. author.&#160;Deng, Chenchen. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="https://doi.org/10.1007/978-981-19-7636-0">https://doi.org/10.1007/978-981-19-7636-0</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Analysis and Design of Networks-on-Chip Under High Process Variation ent://SD_ILS/0/SD_ILS:529355 2025-04-27T19:34:14Z 2025-04-27T19:34:14Z Author&#160;Ezz-Eldin, Rabab. author.&#160;El-Moursy, Magdy Ali. author.&#160;Hamed, Hesham F. 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author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="https://doi.org/10.1007/978-1-4614-1323-3">https://doi.org/10.1007/978-1-4614-1323-3</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Multiprocessor Scheduling for Real-Time Systems ent://SD_ILS/0/SD_ILS:530029 2025-04-27T19:34:14Z 2025-04-27T19:34:14Z Author&#160;Baruah, Sanjoy. author.&#160;Bertogna, Marko. author.&#160;Buttazzo, Giorgio. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="https://doi.org/10.1007/978-3-319-08696-5">https://doi.org/10.1007/978-3-319-08696-5</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Engineering Embedded Systems Physics, Programs, Circuits ent://SD_ILS/0/SD_ILS:530011 2025-04-27T19:34:14Z 2025-04-27T19:34:14Z Author&#160;Hintenaus, Peter. author.&#160;SpringerLink (Online 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Author&#160;Topaloglu, Rasit O. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="https://doi.org/10.1007/978-1-4939-2163-8">https://doi.org/10.1007/978-1-4939-2163-8</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> FPGA Based Accelerators for Financial Applications ent://SD_ILS/0/SD_ILS:529547 2025-04-27T19:34:14Z 2025-04-27T19:34:14Z Author&#160;De Schryver, Christian. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="https://doi.org/10.1007/978-3-319-15407-7">https://doi.org/10.1007/978-3-319-15407-7</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Multi-Net Optimization of VLSI Interconnect ent://SD_ILS/0/SD_ILS:529553 2025-04-27T19:34:14Z 2025-04-27T19:34:14Z Author&#160;Moiseev, Konstantin. author.&#160;Kolodny, Avinoam. author.&#160;Wimer, Shmuel. author.&#160;SpringerLink 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