Search Results for System design - Narrowed by: Logic design. SirsiDynix Enterprise https://katalog.hacettepe.edu.tr/client/en_US/default/default/qu$003dSystem$002bdesign$0026qf$003dSUBJECT$002509Subject$002509Logic$002bdesign.$002509Logic$002bdesign.$0026te$003dILS$0026ps$003d300?dt=list 2024-10-09T01:23:47Z Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers ent://SD_ILS/0/SD_ILS:334136 2024-10-09T01:23:47Z 2024-10-09T01:23:47Z Author&#160;Ayala, Jos&eacute; L. editor.&#160;Shang, Delong. editor.&#160;Yakovlev, Alex. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE(334136.1)<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-3-642-36157-9">http://dx.doi.org/10.1007/978-3-642-36157-9</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers ent://SD_ILS/0/SD_ILS:193696 2024-10-09T01:23:47Z 2024-10-09T01:23:47Z Author&#160;Leuken, Ren&eacute;. editor.&#160;Sicard, Gilles. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-3-642-17752-1">http://dx.doi.org/10.1007/978-3-642-17752-1</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings ent://SD_ILS/0/SD_ILS:195562 2024-10-09T01:23:47Z 2024-10-09T01:23:47Z Author&#160;Ayala, Jos&eacute; L. editor.&#160;Garc&iacute;a-C&aacute;mara, Braulio. editor.&#160;Prieto, Manuel. editor.&#160;Ruggiero, Martino. editor.&#160;Sicard, Gilles. editor.<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-3-642-24154-3">http://dx.doi.org/10.1007/978-3-642-24154-3</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers ent://SD_ILS/0/SD_ILS:191802 2024-10-09T01:23:47Z 2024-10-09T01:23:47Z Author&#160;Monteiro, Jos&eacute;. editor.&#160;Leuken, Ren&eacute;. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-3-642-11802-9">http://dx.doi.org/10.1007/978-3-642-11802-9</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Electronics System Design Techniques for Safety Critical Applications ent://SD_ILS/0/SD_ILS:170397 2024-10-09T01:23:47Z 2024-10-09T01:23:47Z Author&#160;Sterpone, Luca. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-1-4020-8979-4">http://dx.doi.org/10.1007/978-1-4020-8979-4</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Introduction to Embedded System Design Using Field Programmable Gate Arrays ent://SD_ILS/0/SD_ILS:175875 2024-10-09T01:23:47Z 2024-10-09T01:23:47Z Author&#160;Dubey, Rahul. author.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-1-84882-016-6">http://dx.doi.org/10.1007/978-1-84882-016-6</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers ent://SD_ILS/0/SD_ILS:189565 2024-10-09T01:23:47Z 2024-10-09T01:23:47Z Author&#160;Svensson, Lars. editor.&#160;Monteiro, Jos&eacute;. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-3-540-95948-9">http://dx.doi.org/10.1007/978-3-540-95948-9</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedings ent://SD_ILS/0/SD_ILS:187155 2024-10-09T01:23:47Z 2024-10-09T01:23:47Z Author&#160;Az&eacute;mard, Nadine. editor.&#160;Svensson, Lars. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/978-3-540-74442-9">http://dx.doi.org/10.1007/978-3-540-74442-9</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings ent://SD_ILS/0/SD_ILS:184718 2024-10-09T01:23:47Z 2024-10-09T01:23:47Z Author&#160;Vounckx, Johan. editor.&#160;Azemard, Nadine. editor.&#160;Maurine, Philippe. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/11847083">http://dx.doi.org/10.1007/11847083</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Logically determined design clockless system design with NULL convention logic ent://SD_ILS/0/SD_ILS:301645 2024-10-09T01:23:47Z 2024-10-09T01:23:47Z Author&#160;Fant, Karl M.<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://www.contentreserve.com/TitleInfo.asp?ID={1F7D25ED-7DB8-40A3-B98F-A6D66E238591}&Format=50">Click for information</a> <a href="http://proquest.safaribooksonline.com/?fpi=9780471684787">Available by subscription from Safari Books Online</a> John Wiley <a href="http://dx.doi.org/10.1002/0471702897">http://dx.doi.org/10.1002/0471702897</a> MyiLibrary, Table of contents <a href="http://www.myilibrary.com?id=25243&ref=toc">http://www.myilibrary.com?id=25243&ref=toc</a> Volltext <a href="http://proquest.tech.safaribooksonline.de/9780471684787">http://proquest.tech.safaribooksonline.de/9780471684787</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/> Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings ent://SD_ILS/0/SD_ILS:183143 2024-10-09T01:23:47Z 2024-10-09T01:23:47Z Author&#160;Paliouras, Vassilis. editor.&#160;Vounckx, Johan. editor.&#160;Verkest, Diederik. editor.&#160;SpringerLink (Online service)<br/>Preferred Shelf Number&#160;ONLINE<br/>Electronic Access&#160;<a href="http://dx.doi.org/10.1007/11556930">http://dx.doi.org/10.1007/11556930</a><br/>Format:&#160;Electronic Resources<br/>Availability&#160;Online Library~1<br/>