Arama Sonu&ccedil;lar&#305; Logic circuits -- Testing. SirsiDynix Enterprise https://katalog.hacettepe.edu.tr/client/tr_TR/default_tr/default_tr/qu$003dLogic$002bcircuits$002b--$002bTesting.$0026ps$003d300? 2024-12-02T02:25:21Z Formal Modeling and Analysis of Timed Systems 21st International Conference, FORMATS 2023, Antwerp, Belgium, September 19-21, 2023, Proceedings ent://SD_ILS/0/SD_ILS:521082 2024-12-02T02:25:21Z 2024-12-02T02:25:21Z Yazar&#160;Petrucci, Laure. editor.&#160;Sproston, Jeremy. editor.&#160;SpringerLink (Online service)<br/>Yer Numaras&#305;&#160;XX(521082.1)<br/>Elektronik Eri&#351;im&#160;<a href="https://doi.org/10.1007/978-3-031-42626-1">https://doi.org/10.1007/978-3-031-42626-1</a><br/>Format:&#160;Elektrnik Kaynak<br/>Durum&#160;&Ccedil;evrimi&ccedil;i K&uuml;t&uuml;phane~1<br/> The VLSI handbook ent://SD_ILS/0/SD_ILS:289331 2024-12-02T02:25:21Z 2024-12-02T02:25:21Z Yazar&#160;Chen, Wai-Kai, 1936-<br/>Yer Numaras&#305;&#160;ONLINE<br/>Elektronik Eri&#351;im&#160;<a href="http://marc.crcnetbase.com/isbn/9781420005967">Distributed by publisher. Purchase or institutional license may be required for access.</a><br/>Format:&#160;Elektrnik Kaynak<br/>Durum&#160;&Ccedil;evrimi&ccedil;i K&uuml;t&uuml;phane~1<br/> Logic testing and design for testability ent://SD_ILS/0/SD_ILS:220153 2024-12-02T02:25:21Z 2024-12-02T02:25:21Z Yazar&#160;Fujiwara, Hideo.<br/>Yer Numaras&#305;&#160;ONLINE<br/>Elektronik Eri&#351;im&#160;IEEE Xplore <a href="http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6267264">http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6267264</a><br/>Format:&#160;Elektrnik Kaynak<br/>Durum&#160;&Ccedil;evrimi&ccedil;i K&uuml;t&uuml;phane~1<br/>