Arama Sonu&ccedil;lar&#305; Logic. - Daralt&#305;lm&#305;&#351;: Computer hardware. SirsiDynix Enterprise https://katalog.hacettepe.edu.tr/client/tr_TR/default_tr/default_tr/qu$003dLogic.$0026qf$003dSUBJECT$002509Konu$002509Computer$002bhardware.$002509Computer$002bhardware.$0026ic$003dtrue$0026ps$003d300$0026isd$003dtrue?dt=list 2024-11-26T11:00:22Z Design, Analysis and Test of Logic Circuits Under Uncertainty ent://SD_ILS/0/SD_ILS:335669 2024-11-26T11:00:22Z 2024-11-26T11:00:22Z Yazar&#160;Krishnaswamy, Smita. author.&#160;Markov, Igor L. author.&#160;Hayes, John P. author.&#160;SpringerLink (Online service)<br/>Yer Numaras&#305;&#160;ONLINE(335669.1)<br/>Elektronik Eri&#351;im&#160;<a href="http://dx.doi.org/10.1007/978-90-481-9644-9">http://dx.doi.org/10.1007/978-90-481-9644-9</a><br/>Format:&#160;Elektrnik Kaynak<br/>Durum&#160;&Ccedil;evrimi&ccedil;i K&uuml;t&uuml;phane~1<br/> VLSI Design and Test 23rd International Symposium, VDAT 2019, Indore, India, July 4&ndash;6, 2019, Revised Selected Papers ent://SD_ILS/0/SD_ILS:486687 2024-11-26T11:00:22Z 2024-11-26T11:00:22Z Yazar&#160;Sengupta, Anirban. editor.&#160;Dasgupta, Sudeb. editor.&#160;Singh, Virendra. editor.&#160;Sharma, Rohit. editor.&#160;Kumar Vishvakarma, Santosh. editor.<br/>Yer Numaras&#305;&#160;ONLINE<br/>Elektronik Eri&#351;im&#160;<a href="https://doi.org/10.1007/978-981-32-9767-8">https://doi.org/10.1007/978-981-32-9767-8</a><br/>Format:&#160;Elektrnik Kaynak<br/>Durum&#160;&Ccedil;evrimi&ccedil;i K&uuml;t&uuml;phane~1<br/> Cyber Physical Systems. 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(orcid)0000-0002-5522-5739&#160;Ferreira, Pedro M. editor. (orcid)0000-0003-2369-0115&#160;SpringerLink (Online service)<br/>Yer Numaras&#305;&#160;ONLINE<br/>Elektronik Eri&#351;im&#160;<a href="https://doi.org/10.1007/978-3-319-92432-8">https://doi.org/10.1007/978-3-319-92432-8</a><br/>Format:&#160;Elektrnik Kaynak<br/>Durum&#160;&Ccedil;evrimi&ccedil;i K&uuml;t&uuml;phane~1<br/> Software Engineering and Formal Methods SEFM 2017 Collocated Workshops: DataMod, FAACS, MSE, CoSim-CPS, and FOCLASA, Trento, Italy, September 4-5, 2017, Revised Selected Papers ent://SD_ILS/0/SD_ILS:402522 2024-11-26T11:00:22Z 2024-11-26T11:00:22Z Yazar&#160;Cerone, Antonio. editor. (orcid)0000-0003-2691-5279&#160;Roveri, Marco. editor. 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Power and Timing Modeling, Optimization and Simulation 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers ent://SD_ILS/0/SD_ILS:191802 2024-11-26T11:00:22Z 2024-11-26T11:00:22Z Yazar&#160;Monteiro, Jos&eacute;. editor.&#160;Leuken, Ren&eacute;. editor.&#160;SpringerLink (Online service)<br/>Yer Numaras&#305;&#160;ONLINE<br/>Elektronik Eri&#351;im&#160;<a href="http://dx.doi.org/10.1007/978-3-642-11802-9">http://dx.doi.org/10.1007/978-3-642-11802-9</a><br/>Format:&#160;Elektrnik Kaynak<br/>Durum&#160;&Ccedil;evrimi&ccedil;i K&uuml;t&uuml;phane~1<br/> Correct Hardware Design and Verification Methods 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbr&uuml;cken, Germany, October 3-6, 2005. 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