Arama Sonuçları Optimization. - Daraltılmış: Logic design.SirsiDynix Enterprisehttps://katalog.hacettepe.edu.tr/client/tr_TR/default_tr/default_tr/qu$003dOptimization.$0026qf$003dSUBJECT$002509Konu$002509Logic$002bdesign.$002509Logic$002bdesign.$0026ps$003d300?dt=list2025-12-05T15:03:58ZSimulation and Optimization of Digital Circuits Considering and Mitigating Destabilizing Factorsent://SD_ILS/0/SD_ILS:3990902025-12-05T15:03:58Z2025-12-05T15:03:58ZYazar Melikyan, Vazgen. author. SpringerLink (Online service)<br/>Yer Numarası ONLINE<br/>Elektronik Erişim <a href="https://doi.org/10.1007/978-3-319-71637-4">https://doi.org/10.1007/978-3-319-71637-4</a><br/>Format: Elektrnik Kaynak<br/>Durum Çevrimiçi Kütüphane~1<br/>Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papersent://SD_ILS/0/SD_ILS:3341362025-12-05T15:03:58Z2025-12-05T15:03:58ZYazar Ayala, José L. editor. Shang, Delong. editor. Yakovlev, Alex. editor. SpringerLink (Online service)<br/>Yer Numarası ONLINE(334136.1)<br/>Elektronik Erişim <a href="http://dx.doi.org/10.1007/978-3-642-36157-9">http://dx.doi.org/10.1007/978-3-642-36157-9</a><br/>Format: Elektrnik Kaynak<br/>Durum Çevrimiçi Kütüphane~1<br/>Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedingsent://SD_ILS/0/SD_ILS:1955622025-12-05T15:03:58Z2025-12-05T15:03:58ZYazar Ayala, José L. editor. García-Cámara, Braulio. editor. Prieto, Manuel. editor. Ruggiero, Martino. editor. Sicard, Gilles. editor.<br/>Yer Numarası ONLINE<br/>Elektronik Erişim <a href="http://dx.doi.org/10.1007/978-3-642-24154-3">http://dx.doi.org/10.1007/978-3-642-24154-3</a><br/>Format: Elektrnik Kaynak<br/>Durum Çevrimiçi Kütüphane~1<br/>Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papersent://SD_ILS/0/SD_ILS:1936962025-12-05T15:03:58Z2025-12-05T15:03:58ZYazar Leuken, René. editor. Sicard, Gilles. editor. SpringerLink (Online service)<br/>Yer Numarası ONLINE<br/>Elektronik Erişim <a href="http://dx.doi.org/10.1007/978-3-642-17752-1">http://dx.doi.org/10.1007/978-3-642-17752-1</a><br/>Format: Elektrnik Kaynak<br/>Durum Çevrimiçi Kütüphane~1<br/>Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papersent://SD_ILS/0/SD_ILS:1918022025-12-05T15:03:58Z2025-12-05T15:03:58ZYazar Monteiro, José. editor. Leuken, René. editor. SpringerLink (Online service)<br/>Yer Numarası ONLINE<br/>Elektronik Erişim <a href="http://dx.doi.org/10.1007/978-3-642-11802-9">http://dx.doi.org/10.1007/978-3-642-11802-9</a><br/>Format: Elektrnik Kaynak<br/>Durum Çevrimiçi Kütüphane~1<br/>Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papersent://SD_ILS/0/SD_ILS:1895652025-12-05T15:03:58Z2025-12-05T15:03:58ZYazar Svensson, Lars. editor. Monteiro, José. editor. SpringerLink (Online service)<br/>Yer Numarası ONLINE<br/>Elektronik Erişim <a href="http://dx.doi.org/10.1007/978-3-540-95948-9">http://dx.doi.org/10.1007/978-3-540-95948-9</a><br/>Format: Elektrnik Kaynak<br/>Durum Çevrimiçi Kütüphane~1<br/>Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedingsent://SD_ILS/0/SD_ILS:1871552025-12-05T15:03:58Z2025-12-05T15:03:58ZYazar Azémard, Nadine. editor. Svensson, Lars. editor. SpringerLink (Online service)<br/>Yer Numarası ONLINE<br/>Elektronik Erişim <a href="http://dx.doi.org/10.1007/978-3-540-74442-9">http://dx.doi.org/10.1007/978-3-540-74442-9</a><br/>Format: Elektrnik Kaynak<br/>Durum Çevrimiçi Kütüphane~1<br/>Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedingsent://SD_ILS/0/SD_ILS:1847182025-12-05T15:03:58Z2025-12-05T15:03:58ZYazar Vounckx, Johan. editor. Azemard, Nadine. editor. Maurine, Philippe. editor. SpringerLink (Online service)<br/>Yer Numarası ONLINE<br/>Elektronik Erişim <a href="http://dx.doi.org/10.1007/11847083">http://dx.doi.org/10.1007/11847083</a><br/>Format: Elektrnik Kaynak<br/>Durum Çevrimiçi Kütüphane~1<br/>Global Optimization and Constraint Satisfaction Second International Workshop, COCOS 2003, Lausanne, Switzerland, November 18-21, 2003, Revised Selected Papersent://SD_ILS/0/SD_ILS:1831062025-12-05T15:03:58Z2025-12-05T15:03:58ZYazar Jermann, Christophe. editor. Neumaier, Arnold. editor. Sam, Djamila. editor. SpringerLink (Online service)<br/>Yer Numarası ONLINE<br/>Elektronik Erişim <a href="http://dx.doi.org/10.1007/b136292">http://dx.doi.org/10.1007/b136292</a><br/>Format: Elektrnik Kaynak<br/>Durum Çevrimiçi Kütüphane~1<br/>Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedingsent://SD_ILS/0/SD_ILS:1831432025-12-05T15:03:58Z2025-12-05T15:03:58ZYazar Paliouras, Vassilis. editor. Vounckx, Johan. editor. Verkest, Diederik. editor. SpringerLink (Online service)<br/>Yer Numarası ONLINE<br/>Elektronik Erişim <a href="http://dx.doi.org/10.1007/11556930">http://dx.doi.org/10.1007/11556930</a><br/>Format: Elektrnik Kaynak<br/>Durum Çevrimiçi Kütüphane~1<br/>