Arama Sonuçları Syntax. - Daraltılmış: Processor Architectures.
SirsiDynix Enterprise
https://katalog.hacettepe.edu.tr/client/tr_TR/default_tr/default_tr/qu$003dSyntax.$0026qf$003dSUBJECT$002509Konu$002509Processor$002bArchitectures.$002509Processor$002bArchitectures.$0026ps$003d300?dt=list
2026-03-21T23:37:02Z
Formal Verification of Simulink/Stateflow Diagrams A Deductive Approach
ent://SD_ILS/0/SD_ILS:616485
2026-03-21T23:37:02Z
2026-03-21T23:37:02Z
Yazar Zhan, Naijun. author. Wang, Shuling. author. (orcid)0000-0002-2798-2660 Zhao, Hengjun. author. SpringerLink (Online service)<br/>Yer Numarası ONLINE<br/>Elektronik Erişim <a href="https://doi.org/10.1007/978-3-319-47016-0">https://doi.org/10.1007/978-3-319-47016-0</a><br/>Format: Elektrnik Kaynak<br/>Durum Çevrimiçi Kütüphane~1<br/>
SystemVerilog Assertions and Functional Coverage Guide to Language, Methodology and Applications
ent://SD_ILS/0/SD_ILS:612282
2026-03-21T23:37:02Z
2026-03-21T23:37:02Z
Yazar Mehta, Ashok B. author. SpringerLink (Online service)<br/>Yer Numarası ONLINE<br/>Elektronik Erişim <a href="https://doi.org/10.1007/978-3-319-30539-4">https://doi.org/10.1007/978-3-319-30539-4</a><br/>Format: Elektrnik Kaynak<br/>Durum Çevrimiçi Kütüphane~1<br/>