Introduction

Needs of a complete and efficient design environment

Design flow with ESys.NET

Simulation flow with ESys.NET

Observer based verification flow with ESys.NET

Conclusion and book organization

References

Part I: MODELING AND SPECIFICATION

l. H-level requirements engineering for electronic system-level design

1.1. Introduction

1.2. Background

1.2.1 Framework

1.2.2 Software Engineering Approaches

1.3. Proposed Solution

1.3.1 Formalism

1.3.2 Linguistic Pre-Processing

1.3.3 Consistency Validation

1.3.4 Elicitation of Missing Functionalities

1.4. Experimental Results

1.4.1 Automatic Door Controller

1.4.2 Industrial Router

1.4.3 RapidIO

1.5. Linking to a UML-Based Methodology

1.5.1 Integrated Methodology

1.5.2 Case Study

1.6. Conclusion

2. Transaction Level Modeling with .Net

2.1. Introduction

2.2. Transaction Level Modeling

2.3. Abstract Model

2.4. XML Abstract Model Representation

2.5. Simulation Model Generation

2.6. TLM Expression with .NET

2.7. Conclusion

3. Matching Design Patterns Concepts with Hardware Concepts

3.1. Introduction

3.2. Related Work & Background

3.2.1 Original Patterns

3.2.2 Patterns and Hardware

3.3. Patterns and our Classification System

3.4. Object-Oriented Translations

3.4.1 Translations of Object Properties

3.4.2 Translations of Object Methods

3.4.3 Translations of Polymorphism

3.5. Constraints and Assumptions

3.5.1 Constraint: Dynamism of the Hardware

3.5.2 Assumptions: Pattern Automatic Recognition Problem

3.6. Design Pattern Mappings

3.6.1 Creational Patterns

3.6.2 Structural Patterns

3.6.3 Behavioral Patterns

3.7. Conclusion

PART II: SIMULATION

4. A Service Oriented Simulation framework Using .Net Technologies

4.1. Introduction

4.2. Earlier versions of ESyS.Net

4.3. SoCML

4.3.1 Separation of Concerns

4.3.2 Service Oriented Modeling Language

4.3.3 MOC Modeling

4.4. ESyS.Net 3

4.4.1 Model Elaboration

4.4.2 Simulation Core

4.5. Conclusion

5. Co-simulation of Multi-Language Descriptions of Heterogeneous Systems

5.1. Introduction

5.2. Methods Overview for Co-simulation

5.2.1 TCP/IP

5.2.2 Shared Memory

5.2.3 Pinvoke DLL

5.2.4 Component Object Model (COM)

5.2.5 Static Function

5.2.6 The Managed Wrapper

5.3. Simulation of Multi-Language Descriptions of Heterogeneous Systems

5.3.1 Simulation Flow

5.3.2 RTL level

5.3.3 TLM level

5.3.4 Example for Compiled Model

5.3.5 Comparison between New Methodologies and Standard Co-Simulation

5.4. Conclusion

PART III VERIFICATION

6. Implementing LTL Based Verification Through Reflection

6.1. Introduction

6.2. Conclusion

7. Timing Constraints Verification

7.1. Introduction

7.2. Timing Specification

7.3. MiniMax Timing Specification

7.4. Realizability of Min/Max Timing Specification

7.5. TLM and Timing in TLM

7.6. Conclusion

8. Extension of Esys.net by System Verilog Assertions

8.1. Introduction

8.2. Representing System Verilog Assertions 3.1 in HOL

8.2.1 The HOL System

8.2.2 Representing Letters and Words in HOL

8.2.3 Representing Syntax in HOL

8.2.4 Formal Semantics in HOL

8.2.5 Proofs in HOL

8.2.6 Mapping from SVA 3.1 to PSL 1.1.

8.3. Translating SVA to w-Automata in HOL

804. Integration of Verification Environment based in SVA in Esys.net

8.5. Conclusion

PART VI: SYNTHESIS AND IMPLEMENTATION

9. OS Space Exploration and Software Synthesis

9.1. Introduction

9.2. OS Selection

9.3. OS Services' Refinement

9 A. Writing Modem and Portable OS

9.5. Abstracting the OS

9.6. Conclusion

10. Design and Implementation of a CIL Processor for Embedded Applications

10.1. Introduction

10.2. The Conception of Micro-Architecture, Micro-Program and Micro-Instructions

10.3. An Implementation of Micro-Architecture for CIL

10.3.1 CIL and SCIL

10.3.2 Micro-program (Micro-Instructions) for this Implementation

10.3.3 The Architecture of CIL processor

10.3.4 Performance

11. Conclusion

References

Index