chapter 1 Automatic VHDL Model Generation of Parameterized FIR Filters / chapter 2 An LUT-Based High Level Synthesis Framework for Recon?gurable Architectures / chapter 3 Highly Efficient Scalable Parallel-Pipelined Architectures for Discrete Wavelet Transforms / chapter 4 Stride Permutation Access in Interleaved Memory Systems / chapter 5 On Modeling Intra-Task Parallelism in Task-Level Parallel Embedded Systems / chapter 6 Energy Estimation and Optimization for Piecewise Regular Processor Arrays / chapter 7 Automatic Synthesis of Efficient Interfaces for Compiled Regular Architectures / chapter 8 Goal-Driven Recon?guration of Polymorphous Architectures / chapter 9 Realizations of the Extended Linearization Model / chapter 10 Communication Services for Networks on Chip / chapter 11 Single-Chip Multiprocessing for Consumer Electronics -- chapter 12 Future Directions of Programmable and Recon?gurable Embedded Processors