part Part I: Introduction -- chapter 1 Introduction to Physical Design -- chapter 2 Layout Synthesis: A Retrospective -- chapter 3 Metrics Used in Physical Design -- part Part II: Foundations -- chapter 4 Basic Data Structures -- chapter 5 Basic Algorithmic Techniques -- chapter 6 Optimization Techniques for Circuit Design Applications -- chapter 7 Partitioning and Clustering -- part Part III: Floorplanning -- chapter 8 Floorplanning: Early Research -- chapter 9 Slicing Floorplans -- chapter 10 Floorplan Representations -- chapter 11 Packing Floorplan Representations -- chapter 12 Recent Advances in Floorplanning -- chapter 13 Industrial Floorplanning and Prototyping -- part Part IV: Placement -- chapter 14 Placement: Introduction/Problem Formulation -- chapter 15 Partitioning-Based Methods -- chapter 16 Placement Using Simulated Annealing -- chapter 17 Analytical Methods in Placement -- chapter 18 Force-Directed and Other Continuous Placement Methods -- chapter 19 Enhancing Placement with Multilevel Techniques -- chapter 20 Legalization and Detailed Placement -- chapter 21 Timing-Driven Placement -- chapter 22 Congestion-Driven Physical Design -- part Part V: Net Layout and Optimization -- chapter 23 Global Routing Formulation and Maze Routing -- chapter 24 Minimum Steiner Tree Construction* -- chapter 25 Timing-Driven Interconnect Synthesis -- chapter 26 Buffer Insertion Basics -- chapter 27 Generalized Buffer Insertion -- chapter 28 Buffering in the Layout Environment -- chapter 29 Wire Sizing -- part Part VI: Routing Multiple Signal Nets -- chapter 30 Estimation of Routing Congestion -- chapter 31 Rip-Up and Reroute -- chapter 32 Optimization Techniques in Routing -- chapter 33 Global Interconnect Planning -- chapter 34 Coupling Noise -- part Part VII: Manufacturability and Detailed Routing -- chapter 35 Modeling and Computational Lithography -- chapter 36 CMP Fill Synthesis: A Survey of Recent Studies -- chapter 37 Yield Analysis and Optimization -- chapter 38 Manufacturability-Aware Routing -- part Part VIII: Physical Synthesis -- chapter 39 Placement-Driven Synthesis Design Closure Tool -- chapter 40 X Architecture Place and Route: Physical Design for the X Interconnect Architecture -- part Part IX: Designing Large Global Nets -- chapter 41 Inductance Effects in Global Nets -- chapter 42 Clock Network Design: Basics -- chapter 43 Practical Issues in Clock Network Design -- chapter 44 Power Grid Design -- part Part X: Physical Design for Specialized Technologies -- chapter 45 Field-Programmable Gate Array Architectures -- chapter 46 FPGA Technology Mapping, Placement, and Routing -- chapter 47 Physical Design for Three-Dimensional Circuits.