Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings

Integrated Circuit Test Engineering Modern Techniques

Complex Computing-Networks Brain-like and Wave-oriented Electrodynamic Algorithms

Semiconductor Modeling For Simulating Signal, Power, and Electromagnetic Integrity

Design of Very High-Frequency Multirate Switched-Capacitor Circuits Extending the Boundaries of CMOS Analog Front-End Filtering

Micromachined Thin-Film Sensors for SOI-CMOS Co-Integration

Wideband Amplifiers

Computation Engineering Applied Automata Theory and Logic

Effective Functional Verification Principles and Processes

Digital Phase Lock Loops Architectures and Applications

Writing Testbenches using System Verilog

Digital Timing Measurements From Scopes and Probes to Timing and Jitter