Formal Methods for Hardware Verification 6th International School on Formal Methods for the Design of Computer, Communication, and Software Systems, SFM 2006, Bertinoro, Italy, May 22-27, 2006, Advanced Lectures

Systemverilog for Verification A Guide to Learning the Testbench Language Features

Leakage in Nanometer CMOS Technologies

Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications

Interconnect Noise Optimization in Nanometer Technologies

Scalable Hardware Verification with Symbolic Simulation

Knowledge Enterprise: Intelligent Strategies in Product Design, Manufacturing, and Management Proceedings of PROLAMAT 2006, IFIP TC5 International Conference, June 15–17, 2006, Shanghai, China

SystemVerilog for Design A Guide to Using SystemVerilog for Hardware Design and Modeling

Platform Based Design at the Electronic System Level Industry Perspectives and Experiences

Ubiquitous and Pervasive Commerce New Frontiers for Electronic Business

Applications of Evolutionary Computing EvoWorkshops 2006: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoINTERACTION, EvoMUSART, and EvoSTOC, Budapest, Hungary, April 10-12, 2006. Proceedings

Rechneraufbau und Rechnerarchitektur