Halbleiter-Leistungsbauelemente Physik, Eigenschaften, Zuverlässigkeit

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings

A Roadmap for Formal Property Verification

CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom Error Analysis and Practical Design

Continuous-Time Signals

Fast, Efficient and Predictable Memory Accesses Optimization Algorithms for Memory Architecture Aware Compilation

Radio Design in Nanometer Technologies

Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms

Integrated Circuit Test Engineering Modern Techniques

Semiconductor Modeling For Simulating Signal, Power, and Electromagnetic Integrity

Design of Very High-Frequency Multirate Switched-Capacitor Circuits Extending the Boundaries of CMOS Analog Front-End Filtering

Systemverilog for Verification A Guide to Learning the Testbench Language Features